欢迎访问ic37.com |
会员登录 免费注册
发布采购

73K324L-28IH/F 参数 Datasheet PDF下载

73K324L-28IH/F图片预览
型号: 73K324L-28IH/F
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片调制解调器 [Single-Chip Modem]
分类和应用: 调制解调器电信电路
文件页数/大小: 30 页 / 239 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
 浏览型号73K324L-28IH/F的Datasheet PDF文件第3页浏览型号73K324L-28IH/F的Datasheet PDF文件第4页浏览型号73K324L-28IH/F的Datasheet PDF文件第5页浏览型号73K324L-28IH/F的Datasheet PDF文件第6页浏览型号73K324L-28IH/F的Datasheet PDF文件第8页浏览型号73K324L-28IH/F的Datasheet PDF文件第9页浏览型号73K324L-28IH/F的Datasheet PDF文件第10页浏览型号73K324L-28IH/F的Datasheet PDF文件第11页  
73K324L  
CCITT V.22bis,V.23,V.22,V.21, Bell 212A  
Single-Chip Modem  
DATA SHEET  
REGISTER ADDRESS TABLE  
ADDRESS  
DATA BIT NUMBER  
REGISTER  
AD2 - AD0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
CONTROL  
REGISTER  
0
MODULATION  
OPTION  
MODULATION MODULATION  
TRANSMIT  
MODE  
2
TRANSMIT  
MODE  
1
TRANSMIT  
MODE  
0
TRANSMIT  
ENABLE  
ANSWER/  
ORIGINATE  
000  
CR0  
TYPE  
1
TYPE  
0
0000=PWR DOWN  
0001=INT SYNCH  
0010=EXT SYNCH  
0011=SLAVE SYNCH  
0100=ASYCH 8 BITS/CHAR  
0101=ASYCH 9 BITS/CHAR  
0110=ASYCH 10 BITS/CHAR  
0111=ASYCH 11 BITS/CHAR  
1X00=FSK  
0=DISABLE  
TXA OUTPUT 1=ORIGINATE  
0=ANSWER  
10=QAM  
00=DPSK  
01=FSK  
QAM: 0=2400 BIT/S  
DPSK: 0=1200 BIT/S  
1=600 BIT/S  
1=ENABLE  
in V.23  
TXA OUTPUT 0=BC xmit  
1=MC xmit  
FSK: 0=V.23  
1=V.21  
BYPASS  
CONTROL  
REGISTER  
1
TRANSMIT  
PATTERN  
1
TRANSMIT  
PATTERN  
0
ENABLE  
DETECT  
INTERRUPT  
CLK  
CONTROL  
TEST  
MODE  
1
TEST  
MODE  
0
SCRAMBLER/  
ADD PH. EQ.  
(V.23)  
CR1  
001  
RESET  
00=TX DATA  
01=TX ALTERNATE  
10=TX MARK  
0=OFF  
1=ON  
0=NORMAL  
1=BYPASS  
SCRAMBLER RATE OUTPUT  
AT CLK PIN IN  
0=XTAL  
1=16 X DATA  
0=NORMAL  
1=RESET  
00=NORMAL  
01=ANALOG LOOPBACK  
10=REMOTE DIGITAL  
LOOPBACK  
11=TX SPACE  
QAM/DPSK  
MODE ONLY  
11=LOCAL DIGITAL  
LOOPBACK  
UNSCR.  
CARRIER  
MARKS  
DETECT  
DETECT  
SPECIAL  
TONE  
DETECT  
CP  
TONE  
DETECT  
SIGNAL  
QUALITY  
INDICATOR  
RECEIVE  
LEVEL  
INDICATOR  
DETECT  
REGISTER  
S1 PATTERN  
DETECT  
RECEIVE  
DATA  
DR  
010  
0=SIGNAL  
BELOW  
THRESHOLD  
0=NOT PRESENT OUTPUTS  
0=CONDITION NOT DETECTED  
1=CONDITION DETECTED  
0=GOOD  
1=BAD  
1=PATTERN  
FOUND  
RECEIVED  
DATA STREAM  
1=ABOVE  
THRESHOLD  
DTMF0/  
GUARD/  
ANSWER/  
CALLING/SCT  
TRANSMIT  
GUARD/  
CALLING/  
SCT TONE  
RXD  
OUTPUT  
CONTROL  
TRANSMIT  
ANSWER  
TONE  
DTMF2/  
4 WIRE  
FDX  
DTMF1/  
OVERSPEED  
TONE  
CONTROL  
REGISTER  
TRANSMIT  
DTMF  
DTMF3  
TR  
011  
4 BIT CODE FOR 1 OF 16  
DUAL TONE COMBINATIONS  
1=TX DTMF  
RXD PIN  
0=NORMAL  
1=TRI-STATE  
0=OFF  
1=ON  
0=OFF  
1=ON  
GUARD: 0 - 1800 HZ  
1 - 550 HZ  
ANSWER: 0 - 2225 HZ  
1 - 2100 HZ  
0=NORMAL OPERATION  
1=ALLOWS V.23 FULL  
DUPLEX OPERATION  
CALLING: 0 - 1300 HZ  
SCT:  
1 - 900 HZ  
SPECIAL  
REGISTER  
ACCESS  
CONTROL  
REGISTER  
2
CALL  
INITIALIZE  
EQUALIZER  
ENABLE  
RESET  
DSP  
TRAIN  
INHIBIT  
TRANSMIT  
S1  
16 WAY  
MUST BE 0  
CR2  
100  
0=ADAPT EQ  
IN INIT  
1=ADAPT EQ  
OK TO ADAPT  
0=NORMAL  
DOTTING  
1=S1  
0=RX=TX  
1=RX=16 WAY  
0=DSP  
INACTIVE  
1=DSP  
0=ADAPT EQ  
ACTIVE  
1=ADAPT EQ  
FROZEN  
0=ACCESS CR3 0=DSP IN  
1=ACCESS  
SPECIAL  
DEMOD MODE  
1=DSP IN CALL  
PROGRESS  
MODE  
ACTIVE  
REGISTER  
TRANSMIT  
ATTEN.  
1
TRANSMIT  
ATTEN.  
0
CONTROL  
REGISTER  
3
RECEIVE  
GAIN  
BOOST  
TRANSMIT  
ATTEN.  
3
TRANSMIT  
ATTEN.  
2
TRISTATE  
TX/RXCLK  
CR3  
101  
TXDALT  
0
0=CLOCK  
DRIVEN  
1=CLOCK  
TRISTATE  
ALTERNATE  
TRANSMIT  
DATA  
0=NO BOOST  
1=18 dB BOOST  
0000-1111, SETS  
TRANSMIT ATTENUATOR  
16 dB RANGE  
SOURCE  
DEFAULT=0100 ³ -10 dbM0  
SPECIAL  
REGISTER  
TX BAUD  
CLOCK  
RX UNSCR.  
DATA  
TXD  
SOURCE  
SQ  
SELECT1  
SQ  
SELECT0  
0
0
0
101  
SR  
OUTPUTS  
TXBAUD  
CLOCK  
OUTPUTS  
UNSCR.  
DATA  
0=TXD PIN  
1=TX DATA  
CR3-D7  
-5  
-6  
-4  
-3  
00³10  
01³10  
10³10  
11³10  
BER  
BER  
BER  
BER  
ID  
10  
110  
1
1
1
0
X
X
X
X
REGISTER  
00XX=73K212AL, 322L, 321L  
01XX=73K221AL, 302L  
10XX=73K222AL, 222BL  
1100=73K224L  
1110=73K324L  
1100=73K224BL  
1110=73K324BL  
Page: 7 of 30  
© 2005, 2008 TERIDIAN Semiconductor Corporation  
Rev 7.1