Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Tables
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles.......................................................11
Table 2: ADC Resolution.............................................................................................................................12
Table 3: ADC RAM Locations.....................................................................................................................12
Table 4: XRAM Locations for ADC Results ................................................................................................15
Table 5: Meter Equations............................................................................................................................16
Table 6: CKMPU Clock Frequencies ..........................................................................................................19
Table 7: Memory Map .................................................................................................................................20
Table 8: Internal Data Memory Map ...........................................................................................................21
Table 9: Special Function Register Map.....................................................................................................21
Table 10: Generic 80515 SFRs - Location and Reset Values....................................................................22
Table 11: PSW Bit Functions (SFR 0xD0).....................................................................................................23
Table 12: Port Registers .............................................................................................................................24
Table 13: Stretch Memory Cycle Width ......................................................................................................24
Table 14: 71M6531D/F and 71M6532D/F Specific SFRs...........................................................................24
Table 15: Baud Rate Generation ................................................................................................................26
Table 16: UART Modes...............................................................................................................................26
Table 17: The S0CON (UART0) Register (SFR 0x98).................................................................................27
Table 18: The S1CON (UART1) register (SFR 0x9B)..................................................................................27
Table 19: PCON Register Bit Description (SFR 0x87) ................................................................................28
Table 20: Timers/Counters Mode Description ............................................................................................28
Table 21: Allowed Timer/Counter Mode Combinations ..............................................................................29
Table 22: TMOD Register Bit Description (SFR 0x89)................................................................................29
Table 23: The TCON Register Bit Functions (SFR 0x88)............................................................................29
Table 24: The IEN0 Bit Functions (SFR 0xA8)............................................................................................30
Table 25: The IEN1 Bit Functions (SFR 0xB8)............................................................................................31
Table 26: The IEN2 Bit Functions (SFR 0x9A)............................................................................................31
Table 27: TCON Bit Functions (SFR 0x88) .................................................................................................31
Table 28: The T2CON Bit Functions (SFR 0xC8)........................................................................................31
Table 29: The IRCON Bit Functions (SFR 0xC0)........................................................................................31
Table 30: External MPU Interrupts..............................................................................................................32
Table 31: Interrupt Enable and Flag Bits ....................................................................................................32
Table 32: Interrupt Priority Level Groups....................................................................................................33
Table 33: Interrupt Priority Levels...............................................................................................................33
Table 34: Interrupt Priority Registers (IP0 and IP1) ....................................................................................34
Table 35: Interrupt Polling Sequence..........................................................................................................34
Table 36: Interrupt Vectors..........................................................................................................................34
Table 37: Clock System Summary..............................................................................................................36
Table 38: Bank Switching with FL_BANK[2:0] ............................................................................................40
Table 39: Data/Direction Registers and Internal Resources for DIO 1-15 (71M6531D/F) .........................42
Table 40: Data/Direction Registers and Internal Resources for DIO 17-29 (71M6531D/F) .......................42
Table 41: Data/Direction Registers and Internal Resources for DIO 43-46 (71M6531D/F) .......................42
Table 42: Data/Direction Registers and Internal Resources for DIO 1-15 (71M6532D/F) .........................43
Table 43: Data/Direction Registers and Internal Resources for DIO 16-30 (71M6532D/F) .......................43
Table 44: Data/Direction Registers and Internal Resources for DIO 40-51 (71M6532D/F) .......................44
Table 45: DIO_DIR Control Bit ....................................................................................................................44
Table 46: Selectable Control using DIO_DIR Bits .........................................................................................44
Table 47: EECTRL Bits for 2-pin Interface...................................................................................................47
Table 48: EECTRL Bits for the 3-Wire Interface..........................................................................................48
Table 49: SPI Command Description..........................................................................................................50
Table 50: I/O RAM Registers Accessible via SPI .......................................................................................50
Table 51: TMUX[4:0] Selections .................................................................................................................53
Table 52: Available Circuit Functions..........................................................................................................57
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