FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
Pulses
IRQ
Processed
Metering
Data
CE
MPU
Data
Samples
Pre-
Processor
Post-
Processor
I/O RAM (Configuration RAM)
Figure 26: MPU/CE Data Flow
2.7
CE/MPU Communication
Figure 27 shows the functional relationships between the CE and the MPU. The CE is controlled by the
MPU via shared registers in the I/O RAM and in RAM.
The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY, which are connected to
the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively
processing data. This signal will occur once every multiplexer cycle. XFER_BUSY indicates that the CE
is updating data to the output region of the RAM. This will occur whenever the CE has finished generat-
ing a sum by completing an accumulation interval determined by SUM_CYCLES * PRE_SAMPS samples.
Interrupts to the MPU occur on the falling edges of the XFER_BUSY and CE_BUSY signals.
Refer to Section 4.3 CE Interface Description for additional information on setting up the device using the
MPU firmware.
VAR
(DIO7)
PULSES
W (DIO6)
DISPLAY (Memory
mapped LCD
segments)
APULSEW
APULSER
EXT PULSE
SERIAL
(UART0/1)
SAG CONTROL
MPU
EEPROM
(I2C)
SAMPLES
ADC
DATA
CE BUSY
CE
DIO
XFER BUSY
INTERRUPTS
Mux Control
I/O RAM (Configuration RAM)
Figure 27: MPU/CE Communication
v1.2
© 2005-2009 TERIDIAN Semiconductor Corporation
61
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
