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71M6532F 参数 Datasheet PDF下载

71M6532F图片预览
型号: 71M6532F
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量IC [Energy Meter IC]
分类和应用:
文件页数/大小: 115 页 / 2363 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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FDS 6531/6532 005  
Data Sheet 71M6531D/F-71M6532D/F  
Figures  
Figure 1: 71M6531D/F IC Functional Block Diagram ...................................................................................8  
Figure 2: 71M6532D/F IC Functional Block Diagram ...................................................................................9  
Figure 3: General Topology of a Chopped Amplifier ..................................................................................13  
Figure 4: CROSS Signal with CHOP_E = 00...............................................................................................13  
Figure 5: AFE Block Diagram (Shown for the 71M6532D/F)......................................................................14  
Figure 6: Samples from Multiplexer Cycle ..................................................................................................17  
Figure 7: Accumulation Interval ..................................................................................................................18  
Figure 8: Interrupt Structure........................................................................................................................36  
Figure 9: Optical Interface...........................................................................................................................41  
Figure 10: Connecting an External Load to DIO Pins.................................................................................46  
Figure 11: 3-Wire Interface. Write Command, HiZ=0. ...............................................................................49  
Figure 12: 3-Wire Interface. Write Command, HiZ=1 ................................................................................49  
Figure 13: 3-Wire Interface. Read Command............................................................................................49  
Figure 14: 3-Wire Interface. Write Command when CNT=0......................................................................49  
Figure 15: 3-Wire Interface. Write Command when HiZ=1 and WFR=1. ..................................................50  
Figure 16: SPI Slave Port: Typical Read and Write operations..................................................................51  
Figure 17: Functions defined by V1 ............................................................................................................51  
Figure 18: Voltage, Current, Momentary and Accumulated Energy...........................................................53  
Figure 19: Timing Relationship between ADC MUX, Compute Engine......................................................54  
Figure 20: RTM Output Format...................................................................................................................54  
Figure 21: Operation Modes State Diagram ...............................................................................................55  
Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns ......................58  
Figure 23: Power-Up Timing with V3P3SYS and VBAT tied together........................................................58  
Figure 24: Power-Up Timing with VBAT only..............................................................................................59  
Figure 25: Wake Up Timing ........................................................................................................................60  
Figure 26: MPU/CE Data Flow....................................................................................................................61  
Figure 27: MPU/CE Communication...........................................................................................................61  
Figure 28: Resistive Voltage Divider...........................................................................................................62  
Figure 29: CT with Single Ended (Left) and Differential Input (Right) Connection .....................................62  
Figure 30: Resistive Shunt (Left) and Rogowski Sensor (Right) Connection.............................................62  
Figure 31: Connecting LCDs.......................................................................................................................64  
Figure 32: I2C EEPROM Connection ..........................................................................................................65  
Figure 33: Three-Wire EEPROM Connection.............................................................................................65  
Figure 34: Connections for UART0.............................................................................................................66  
Figure 35: Connection for Optical Components..........................................................................................66  
Figure 36: Voltage Divider for V1................................................................................................................67  
Figure 37: External Components for the RESET Pin: Push-button (Left), Production Circuit (Right) ........67  
Figure 38: External Components for the Emulator Interface ......................................................................68  
Figure 39: Connecting a Battery .................................................................................................................68  
Figure 40: CE Data Flow: Multiplexer and ADC..........................................................................................93  
Figure 41: CE Data Flow: Scaling, Gain Control, Intermediate Variables ..................................................94  
Figure 42: CE Data Flow: Squaring and Summation Stages......................................................................94  
Figure 43: SPI Slave Port (MISSION Mode) Timing.................................................................................103  
Figure 44: Wh Accuracy, 0.1 A to 200 A at 240 V/50 Hz and Room Temperature ..................................104  
Figure 45: QFN-68 Package Outline, Top and Side View ........................................................................105  
Figure 46: QFN-68 Package Outline, Bottom View Table 83: QFN 68 Package Dimensions (in mm) ....105  
Figure 47: Pinout for QFN-68 Package.....................................................................................................106  
Figure 48: PCB Land Pattern for QFN 68 Package..................................................................................107  
Figure 49: PCB Land Pattern for LQFP-100 Package..............................................................................108  
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© 2005-2009 TERIDIAN Semiconductor Corporation  
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