71M6403
Electronic Trip Unit
SEPTEMBER 2006
In a typical application, the I0 through I5 inputs are connected to current transformers or Rogowski coils that sense the current
on each phase of the line voltage.
The Multiplexer Control Circuit handles the setting of the multiplexer. The function of the Multiplexer Control Circuit is governed
by the I/O RAM registers MUX_ALT (0x2005[2]) and MUX_DIV (0x2002[7:6]). MUX_DIV controls the number of samples per
cycle. It can request 2, 3, 4, or 6 multiplexer states per cycle.
Multiplexer Control Circuit also controls the FIR filter initiation and the chopping of the ADC reference voltage, VREF. The
Multiplexer Control Circuit is clocked by PLLOUT, the 32768Hz clock from the PLL block derived from CK, and launches each
pass through the CE program.
ADC
A single 21/22-bit delta-sigma A/D converter digitizes the power inputs to the AFE. The ADC inputs I0 - I5 are referenced to
V3P3A with an input voltage range of ± 250 mv. The resolution of the ADC is programmable using the I/O RAM register
FIR_LEN register (0x2005[4]). ADC resolution may be selected to be 21 bits (FIR_LEN=0), or 22 bits (FIR_LEN=1). Conversion
time is two cycles of PLLOUT with FIR_LEN = 0 and three cycles with FIR_LEN = 1.
Accuracy, timing and functional specifications in this data sheet are based on FIR_LEN = 0 (two PLLOUT cycles).
Initiation of each ADC conversion is controlled by the Multiplexer Control Circuit as described previously.
FIR Filter
The finite impulse response (FIR) filter is an integral part of the ADC and it is optimized for use with the multiplexer. The purpose
of the FIR is to decimate the ADC output to the desired resolution. At the end of each ADC conversion, the output data of the
FIR filter (raw data) is stored into the CE Data RAM (DRAM) location determined by the multiplexer selection. The location of the
raw data in the CE DRAM is specified in the CE Program and Environment Section.
Voltage Reference
The 71M6403 includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques. The reference of
the 71M6403 is trimmed in production to minimize errors caused by component mismatch and drift. The result is a voltage output
with a predictable temperature coefficient.
The voltage reference is chopper stabilized, i.e. the polarity can be switched by the MPU using the I/O RAM register CHOP_ENA
(0x2002[5:4]). The two bits in the CHOP_ENA register enable the MPU to operate the chopper circuit in regular or inverted
operation, or in “toggling” mode. When the chopper circuit is toggled in between multiplexer cycles, DC offsets on the measured
signals will automatically be averaged out.
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© 2006 TERIDIAN Semiconductor Corporation
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TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
