71M6403
Electronic Trip Unit
SEPTEMBER 2006
Figures
Figure 1: IC Functional Block Diagram................................................................................................................................7
Figure 2: General Topology of a Chopped Amplifier..........................................................................................................10
Figure 3: AFE Block Diagram ............................................................................................................................................11
Figure 4: Samples in Multiplexer Cycle.............................................................................................................................12
Figure 5: Memory Map .....................................................................................................................................................14
Figure 6: DIO Ports Block Diagram...................................................................................................................................35
Figure 7: LCD Voltage Boost Circuitry...............................................................................................................................39
Figure 8: V1 Input Voltage Thresholds..............................................................................................................................40
Figure 9: Timing Relationship between ADC MUX, CE, and Serial Transfers .....................................................................44
Figure 10: RTM Output Format.........................................................................................................................................45
Figure 11: SSI Timing, (SSI_FPOL = SSI_RDYPOL = 0) ...................................................................................................45
Figure 12: SSI Timing, 16-bit Field Example (External Device Delays SRDY) ....................................................................45
Figure 13: MPU/CE Data Flow...........................................................................................................................................46
Figure 14: MPU/CE Communication (Functional)..............................................................................................................47
Figure 15: MPU/CE Communication (Processing Sequence) ............................................................................................47
Figure 16: Chop Polarity w/ Automatic Chopping..............................................................................................................48
Tables
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles (EQU = 5).................................................................8
Table 2: CE DRAM Locations for ADC Results..................................................................................................................12
Table 3: Stretch Memory Cycle Width...............................................................................................................................15
Table 4: Internal Data Memory Map..................................................................................................................................16
Table 5: Special Function Registers Locations..................................................................................................................16
Table 6: Special Function Registers Reset Values.............................................................................................................17
Table 7: PSW Register Flags.............................................................................................................................................18
Table 8: PSW bit functions ...............................................................................................................................................18
Table 9: Port Registers.....................................................................................................................................................19
Table 10: Special Function Registers................................................................................................................................20
Table 11: Baud Rate Generation .......................................................................................................................................21
Table 12: UART Modes.....................................................................................................................................................21
Table 13: The S0CON Register .........................................................................................................................................22
Table 14: The S1CON register...........................................................................................................................................22
Table 15: The S0CON Bit Functions ..................................................................................................................................22
Table 16: The S1CON Bit Functions ..................................................................................................................................23
Table 17: The TMOD Register...........................................................................................................................................24
Table 18: TMOD Register Bit Description..........................................................................................................................24
Table 19: Timers/Counters Mode Description...................................................................................................................25
Table 20: The TCON Register............................................................................................................................................25
Table 21: The TCON Register Bit Functions ......................................................................................................................25
Table 22: Timer Modes.....................................................................................................................................................26
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© 2006 TERIDIAN Semiconductor Corporation
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