71M6403
Electronic Trip Unit
SEPTEMBER 2006
On-Chip Resources......................................................................................................................35
DIO Ports .......................................................................................................................35
Physical Memory............................................................................................................36
Real-Time Clock (RTC)..................................................................................................37
Comparators (V2, INEUTRAL).......................................................................................38
LCD Drivers....................................................................................................................38
LCD Voltage Boost Circuitry...........................................................................................38
UART (UART0) and Optical Port (UART1) ....................................................................39
Hardware Reset Mechanisms ........................................................................................39
Reset Pin (RESETZ)......................................................................................................39
Hardware Watchdog Timer ............................................................................................39
Internal Voltages (VBIAS and V2P5)..............................................................................40
Internal Clocks and Clock Dividers.................................................................................41
I2C Interface (EEPROM) ................................................................................................41
Test Ports.......................................................................................................................42
FUNCTIONAL DESCRIPTION ...................................................................................................................44
System Timing Summary .............................................................................................................44
Data Flow .....................................................................................................................................46
CE/MPU Communication..............................................................................................................46
Fault, Reset, Power-Up ................................................................................................................48
Chopping Circuitry........................................................................................................................48
Program Security..........................................................................................................................49
FIRMWARE INTERFACE...........................................................................................................................50
I/O RAM MAP – In Numerical Order.............................................................................................50
SFR MAP (SFRs Specific to TERIDIAN 80515) – In Numerical Order.........................................51
I/O RAM (Configuration RAM) – Alphabetical Order.....................................................................52
CE Program and Environment......................................................................................................58
CE Program ...................................................................................................................58
Formats..........................................................................................................................58
Constants.......................................................................................................................58
Environment...................................................................................................................58
CE Calculations..............................................................................................................59
CE RAM Locations.......................................................................................................................59
CE Front End Data (Raw Data)......................................................................................59
Input Configuration.........................................................................................................60
Accumulation Strobe Output ..........................................................................................60
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© 2006 TERIDIAN Semiconductor Corporation
REV 1.0
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
