PRECISION ANALOG FRONT ENDS
TC500
TC500A
TC510
TC514
Table 1. Internal Analog Gate Status
Internal Analog Gate Status
Conversion Phase
SWI
SWR+I
SWR–I
SWZ
SWR
SW1
SWIZ
Auto-Zero (A = 0, B = 1)
Input Signal Integration
(A = 1, B = 0)
Closed
Closed
Closed
Closed
Reference Voltage
Deintegration (A =1, B= 1)
Integrator Output Zero
(A = 0, B = 0)
Closed*
Closed
Closed
Closed
Closed
*Assumes a positive polarity input signal. SWR–I would be closed for a negative input signal.
Analog Input Signal Integration Phase (INT)
voltage range, common-mode rejection is typically 80dB.
Full accuracy is maintained, however, when the inputs are
no less than 1.5V from either supply.
The TC5xx integrates the differential voltage between
the (VI+N) and (VI–N) inputs. The differential voltage must be
within the device's common-mode range VCMR
.
The integrator output also follows the common-mode
voltage. The integrator output must not be allowed to satu-
rate. A worst-case condition exists, for example, when a
large, positive common-mode voltage with a near full-scale
negative differential input voltage is applied. The negative
input signal drives the integrator positive when most of its
swing has been used up by the positive common-mode
voltage. For these critical applications, the integrator swing
can be reduced. The integrator output can swing within 0.9V
of either supply without loss of linearity.
The input signal polarity is normally checked via soft-
ware at the end of this phase: CMPTR = 1 for positive
polarity; CMPTR = 0 for negative polarity.
Reference Voltage Deintegration Phase (DINT)
The previously charged reference capacitor is con-
nected with the proper polarity to ramp the integrator output
backtozero. Anexternally-provided,precisiontimerisused
to measure the duration of this phase. The resulting time
measurementisproportionaltothemagnitudeoftheapplied
input voltage.
Analog Common
Analog common is used as VIN return during system-
zeroandreferencedeintegrate.IfVI–N isdifferentfromanalog
common, a common-mode voltage exists in the system.
ThissignalisrejectedbytheexcellentCMRoftheconverter.
In most applications, VI–N will be set at a fixed known voltage
(i.e., power supply common). A common-mode voltage will
exist when VI–N is not connected to analog common.
Integrator Output Zero Phase (IZ)
This phase guarantees the integrator output is at 0V
when the Auto Zero phase is entered and that only system
offset voltages are compensated. This phase is used at the
endofthereferencevoltagedeintegrationphaseand MUST
beusedforALLTC5xxapplicationshavingresolutionsof12
bits or more. If this phase is not used, the value of the Auto-
Zero capacitor (CAZ) must be about 2 to 3 times the value of
the integration capacitor (CINT) to reduce the effects of
charge-sharing. The Integrator Output Zero phase should
be programmed to operate until the Output of the Compara-
tor returns "HIGH". The overall Timing System is shown in
Figure 8.
Differential Reference (VR+EF, VR–EF
)
Thereferencevoltagecanbe anywherewithin1Vofthe
power supply voltage of the converter. Roll-over error is
caused by the reference capacitor losing or gaining charge
due to stray capacitance on its nodes. The difference in
reference for (+) or (–) input voltages will cause a roll-over
error. Thiserrorcanbeminimizedbyusingalargereference
capacitor in comparison to the stray capacitance.
ANALOG SECTION
Differential Inputs (VI+N, VI–N)
Phase Control Inputs (A, B)
The TC5xx operates with differential voltages within the
input amplifier common-mode range. The amplifier com-
mon-mode range extends from 1.5V below positive supply
to 1.5V above negative supply. Within this common-mode
The A, B unlatched logic inputs select the TC5xx oper-
ating phase. The A, B inputs are normally driven by a
microprocessor I/O port or external logic.
3-26
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