HV5530
44-Lead PLCC Pin Assignment (PJ)
Pin #
Function
HVOUT16
HVOUT17
HVOUT18
HVOUT19
HVOUT20
HVOUT21
HVOUT22
HVOUT23
HVOUT24
HVOUT25
HVOUT26
HVOUT27
HVOUT28
HVOUT29
HVOUT30
HVOUT31
HVOUT32
DATA OUTPUT
N/C
Description
1
2
3
4
5
6
7
8
9
High voltage outputs.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Data output pin.
No connect.
N/C
N/C
POL
Inverts the polarity of the HVOUT pins
CLK
Clock pin, shift registers shifts data on falling edge of input clock.
Reference voltage, usually ground.
VSS
VDD
Logic supply voltage.
LE
Latch enable pin, data is shifted from shift register to latches on logic input high.
Data input pin.
DATA INPUT
Blanking pin sets all HVOUT pins low or high depending upon state of polarity.
See function table.
28
BL
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
N/C
No connect.
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
HVOUT
1
2
3
4
5
6
7
8
9
High voltage outputs.
HVOUT10
HVOUT11
HVOUT12
HVOUT13
HVOUT14
HVOUT15
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
6
SUPERTEX [ Supertex, Inc ]
