HV4522/HV4622
Functional Block Diagram
VSS
Polarity
Blanking
Latch Enable
Data Input
Clock
Latch
Latch
HVOUT
1
2
HVOUT
32-Bit
Shift
Register
(Outputs 3 to 30
not shown)
Latch
Latch
HVOUT31
HVOUT32
Data Out
Function Table
Inputs
Outputs
Function
Shift Reg
HV Outputs
Data Out
Data
CLK
LE
BL
POL
1
2…32
1
2…32
H…H
L…L
*…*
*
*
*
*
*
*
*
*
*
All on
X
X
X
X
L
L
L
L
H
L
*
*…*
H
L
*
All off
X
X
*
*…*
Invert mode
Load S/R
X
X
H
H
H
H
H
H
*
*…*
H or L
↓
H or L
H or L
↓
L
H
H
L
H or L *…*
*
*…*
Load
latches
X
X
L
↑
*
*
*…*
*…*
*…*
*…*
*
*…*
↑
*
*…*
Transparent
latch mode
H
H
H
H
L
H
L
H
*…*
H
↓
*…*
Notes:
H = high level = -12V, L = low level = 0V, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transition.
* = dependent on previous stage’s state before the last CLK high-to-low transition or last LE high.
4
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