HV430
Truth Table
Logic Inputs*
Output
External N-Channel
NIN
PIN
mode
EN
RESET
External P-Channel
MOSFET
MOSFET
OFF
OFF
ON
L
L
L
H
L
H
H
H
H
L
H
H
H
H
H
H
L
> Vreset(on)
> Vreset(on)
> Vreset(on)
> Vreset(on)
> Vreset(on)
> Vreset(on)
X
OFF
ON
H
H
H
L
OFF
OFF
ON
H
X
X
X
X
OFF
OFF
ON
L
OFF
OFF
OFF
X
X
X
X
OFF
OFF
X
< Vreset(off)
* Unused logic inputs should be connected to VDD or GND.
Block Diagram and Application Circuit
V
PP1
V
DD
+5V
V
PP2
V
V
PP1
PP2
V
DD
FAULT
Regulator
De-glitcher
reset
clk
R
sense
V
V
PSEN
Down
Translator
Current
Trip
P
IN
PGATE
Up
P
Translator
Driver
MODE
NC
NC
Control
Logic
DEADBAND
Ringer
Output
V
NGATE
N
Driver
Up
Translator
N
IN
ENABLE
RESET
V
Down
Translator
Current
Trip
NSEN
V
DD
R
10µA
sense
V
NN1
SIG
GND
PWR
GND
V
NN2
Regulator
V
NN2
V
NN1
Note: PIN, NIN, and ENABLE are internally pulled low. MODE is internally pulled high.
A Reset capacitor in the range of 1-10µF will yield a couple-second turn-on delay. Tantalum is recommended.
4
SUPERTEX [ Supertex, Inc ]
