HV430
Negative High Voltage Output
Symbol
VNgate
RsourceN
RsinkN
triseN
Parameter
Min
Typ
Max
VNN1
15.0
15.0
50
Unit
V
Conditions
No load on VNgate
IOUT=80mA
Output voltage swing
VNN2
VNgate source resistance
VNgate sink resistance
VNgate rise time
Ω
Ω
IOUT=-80mA
ns
ns
Cload=1.0nF
tfallN
VNgate fall time
50
Cload=1.0nF
tpwn(min)
VNgate minimum pulse width
(internally limited)
100
150
200
300
ns
ns
V
tdelayN
VNsen
tshortN
NIN to VNgate delay time
mode=1
VNgate current sense voltage
VNgate current sense OFF time
VNN1+0.85
VNN1+1.0
VNN1+1.15
150
ns
Control Circuitry
Symbol
Parameter
Min
0
Typ
Max
Unit
V
Conditions
VIL
Logic input low voltage
Logic input high voltage
Input pull-down current
Input pull-up resistance
Logic output low voltage
Logic output high voltage
Reset voltage, device off
Reset voltage, device on
Reset hysteresis voltage
Reset pull-up current
RESET on delay
0.60
5.0
5
VDD=5.0V
VDD=5.0V
VIH
2.7
0.5
100
V
IINdn
1
µA
kΩ
V
PIN, NIN, ENABLE
MODE
Rup
200
300
0.50
VOL
VDD=5.0V, IOUT=-0.5mA
VDD=5.0V, IOUT=0.5mA
VDD=5.0V
VOH
4.50
3.2
3.7
0.3
7
V
VRST(OFF)
VRST(ON)
VRST(HYS)
Ireset
3.5
4.0
V
V
VDD=5.0V
V
VDD=5.0V
10
13
1.0
1.0
150
1.0
µA
µs
µs
µs
µs
VRESET=0-4.5V
tRST(ON)
tRST(OFF)
tEN(ON)
tEN(OFF)
RESET off delay
ENABLE on delay
50
100
4
ENABLE off delay
NIN/PIN
cycles
tFLT(HOLD)
tDB
FAULT hold time
Deadband time
ENABLE=1
35
50
70
ns
Mode=0, Rdb=5.6kΩ
105
140
175
300
300
ns
ns
ns
Mode=0, Rdb=18kΩ
Mode=0, Rdb<27kΩ
Mode=0, Rdb<27kΩ
tdelay(N-P)
tdelay(P-N)
N-off to P-on transistion delay
P-off to N-on transistion delay
Delay difference
tdelayN(off) - tdelayP(on)
∆tdelay(N-P)
∆tdelay(P-N)
-80
-80
0
0
80
80
ns
ns
Mode=1
Mode=1
Delay difference
tdelayP(off) - tdelayN(on)
3
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