HV219
Power Up/Down Sequence
1)
Power up/down sequence is arbitrary except GND must be powered up first and powered down last. This applies for
applications powering GND of the IC with different voltages.
2)
3)
Vsig must always be at or in between VPP and VNN or floating during power up/down transition.
Rise and fall times of the power supplies VDD, VPP, and VNN should not be less than 1.0ms.
Logic Truth Table
Data in the 8-bit Shift Register
CL
Output Switch State
LE
D0 D1 D2 D3 D4 D5 D6 D7
SW0
OFF
ON
SW1
SW2
SW3
SW4
SW5
SW6
SW7
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
OFF
ON
H
L
H
OFF
ON
L
H
OFF
ON
L
H
OFF
ON
L
H
OFF
ON
L
H
OFF
ON
L
H
X
X
OFF
ON
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HOLD PREVIOUS STATE
OFF OFF OFF OFF
OFF
OFF
OFF
OFF
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L to H transition clock.
3. The switches go to a state retaining their present condition at the rising edge of the LE .
4. When LE is low, the shift register data flows through the latch.
5. Shift register clocking has no effect on the switch states if LE is high.
6. The clear input overrides all other inputs.
Logic Timing Waveform
D N - 1
D N
DN + 1
DATA
IN
50%
50%
50%
50%
LE
t
WLE
t
SD
50%
50%
CLOCK
t
t
h
SU
t
DD
DATA
OUT
50%
t
t
OFF
ON
VOUTOFF
90%
(TYP)
10%
ON
CLR
50%
50%
tWCL
A042705
5
SUPERTEX [ Supertex, Inc ]
