HV219
Truth Table
Data in 8-Bit Shift Register
Output Switch State
LE
CL
D0 D1 D2 D3 D4 D5 D6 D7
SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
OFF
ON
OFF
H
ON
L
H
OFF
ON
L
H
OFF
ON
L
H
OFF
ON
L
H
OFF
ON
L
H
OFF
ON
L
OFF
H
ON
Hold Previous State
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OFF OFF OFF OFF OFF OFF OFF OFF
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L to H transition clock.
3. The switches go to a state retaining their present condition at the rising edge of the LE.
4. When LE is low, the shift register data flows through the latch.
5. Shift register clocking has no effect on the switch states if LE is high.
6. The clear input overrides all other inputs.
Logic Timing Waveforms
DN+1
DN
DN-1
DATA
IN
50%
50%
50%
50%
tWLE
LE
tSD
50%
50%
CLOCK
tSU
th
tDO
DATA
OUT
50%
tOFF
tON
OFF
VOUT
(typ)
90%
10%
ON
CLR
50%
50%
tWCL
Doc.# DSFP-HV219
C070713
Supertex inc.
www.supertex.com
5
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