HV219
Pin Configuration
Ordering Information
48
1
Part Number
Package Option
Packing
250/Tray
1000/Reel
38/Tube
500/Reel
HV219FG-G
48-Lead LQFP
28-Lead PLCC
HV219FG-G M931
HV219PJ-G
48-Lead LQFP
HV219PJ-G M904
(top view)
-G denotes a lead (Pb)-free / RoHS compliant package
4
1
28
26
Absolute Maximum Ratings
Parameter
Value
VDD logic power supply voltage
VPP - VNN supply voltage
-0.5V to +15V
220V
28-Lead PLCC
(top view)
VPP positive high voltage supply
-0.5V to VNN +200V
+0.5V to -200V
-0.5V to VDD +0.3V
VNN to VPP
V
NN negative high voltage supply
Product Marking
Logic input voltages
Top Marking
Analog signal range
YYWW
HV219FG
LLLLLLLLL
YY = Year Sealed
WW = Week Sealed
L = Lot Number
Peak analog signal current/channel
Storage temperature
3.0A
C = Country of Origin*
A = Assembler ID*
-65OC to +150OC
Bottom Marking
= “Green” Packaging
CCCCCCCC
AAA
Power dissipation:
28-Lead PLCC
48-Lead LQFP
*May be part of top marking
1.2W
1.0W
Package may or may not include the following marks: Si or
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. Continuous operation of the device
at the absolute rating level may affect device reliability. All voltages are referenced to device
ground.
48-Lead LQFP
Top Marking
YY = Year Sealed
YYWW
WW = Week Sealed
HV219PJ
LLLLLLLLLL
L = Lot Number
Operating Conditions
C = Country of Origin*
Bottom Marking
A = Assembler ID*
Sym Parameter
Value
4.5V to 13.2V
40V to VNN +200V
-40V to -160V
VDD -1.5V to VDD
0V to 1.5V
= “Green” Packaging
*May be part of top marking
CCCCCCCCCCC
AAA
VDD Logic power supply voltage
Package may or may not include the following marks: Si or
VPP
Positive high voltage supply
28-Lead PLCC
VNN Negative high voltage supply
VIH
VIL
High level input logic voltage
Low-level input logic voltage
Typical Thermal Resistance
Package
θja
Analog signal voltage
peak-to-peak
48-Lead LQFP
28-Lead PLCC
52OC/W
48OC/W
VSIG
TA
VNN +10V to VPP -10V
0OC to 70OC
Operating free air temperature
Power Up/Down Sequence
1. Power up/down sequence is arbitrary except GND must be powered up first and powered down last. This applies for
applications powering GND of the IC with different voltages.
2. VSIG must always be at or in between VPP and VNN or floating during power up/down transition.
3. Rise and fall times of the power supplies VDD, VPP, and VNN should not be less than 1.0ms.
Doc.# DSFP-HV219
C070713
Supertex inc.
www.supertex.com
2
SUPERTEX [ Supertex, Inc ]
