SMS47
PreliminaryInformation
PIN DESCRIPTIONS
V0, V1, V2, V3 (16, 2, 3, 14)
These inputs are used as the voltage monitor inputs and
as the voltage supply for the SMS47. Internally they are
diode ORed and the input with the highest voltage
potential will be the default supply voltage (VDD_CAP).
V
PTH-UV
V
— V
3
0
t
t
DRST
PRTO
TheRESET#outputwillbevalidifanyoneofthefourinputs
isabove1V. However,forfulldeviceoperationatleastone
of the inputs must be at 2.7V or higher.
RESET#
The sensing threshold for each input is independently
programmable in 5mV increments from 0.6V to 1.875V or
15mV increments from 1.8V to 5.625V. Also, the occur-
renceofanunder-orover-voltageconditionthatisdetected
asaresultofthethresholdsettingcanbeusedtogenerate
a RESET#. The programmable nature of the threshold
voltage eliminates the need for external voltage divider
networks.
Figure 3. RESET# Timing
ration register 4). Refer to Figures 2 and 3 for a detailed
illustrationoftherelationshipbetweenMR#,RESET#and
the VIN levels.
VDD_CAP(12)
TheVDD_CAPpinconnectstotheinternalsupplyvoltage
for the SMS47. A capacitor is placed on this pin to filter
supply noise as well as hold up the device in the event of
powerfailure. Thevoltageonthisnodeisdeterminedbythe
highest input voltage. Loading of this pin should be
minimized to prevent excessive power dissipation in the
part.
GND
Power supply return.
MR# (1)
The manual reset input always generates a RESET#
output whenever it is driven low. The duration of the
RESET#outputpulsewillbeinitiatedwhenMR#goeslow
and it will stay low for the duration of MR# low plus the
programmed reset time-out period (tPRTO). If MR# is
brought low during a power-on cascade of the PUP#s the
cascade will be halted for the reset duration, and will then
resume from the point at which it was interrupted. MR#
mustbeheldlowduringaconfigurationregisterwrite. This
signal is pulled up internally through a 50kΩ resistor.
WLDI(15)
Watchdogtimer input. Ahigh-to-lowtransitionontheWLDI
input will clear the watchdog timer, effectively starting a
new time-out period. This signal is pulled up internally
through a 50kΩ resistor.
If WLDI is stuck low and no high-to-low transition is
received within the programmed tPWDTO period (pro-
grammedwatchdogtime-out)RESET# willbedrivenlow.
Refer to Figure 4 for a detailed illustration.
RESET#(11)
The reset output is an active low open drain output. It will
be driven low whenever the MR# input is low or whenever
anenabledunder-voltageorover-voltageconditionexists.
Thefourvoltagemonitorinputsarealwaysfunctioning,but
theirabilitytogeneratearesetisprogrammable(configu-
Holding WLDI low will not block the watchdog from timing
outandgeneratingareset. RefertoFigure4foradetailed
illustrationoftherelationshipbetweenRESET#andWLDI.
t
0
t
PWDTO
t
t
t
t
0
0
0
0
t
MR#
PRTO
RESET#
WLDI
t
DMRRST
t
t
PWDTO
PRTO
t
RESET#
PRTO
2047 Fig04 3.0
Figure 4. Watchdog and WLDI Timing
Figure 2. RESET# Timing with MR#
SUMMIT MICROELECTRONICS, Inc.
2087 1.1 04/11/05
6
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
