SMS47
PreliminaryInformation
INTERNAL BLOCK DIAGRAM
VDD_CAP
CONFIGURATION
REGISTER
50kΩ
11
RESET#
MR#
1
V
0
16
PROGRAMMABLE
RESET PULSE
GENERATOR
NV DAC
REF
+
–
4
5
PUP#1
PUP#2
PUP#3
PROGRAMMABLE
POWER
CASCADING
V
1
2
3
13
NV DAC
REF
+
–
9
SDA
SERIAL
BUS
V
2
10 SCL
CONTROL
LOGIC
7
A2
A1
NV DAC
REF
6
+
–
PROGRAMMABLE
WATCHDOG
TIMER
V
3
14
NV DAC
REF
VDD_CAP
+
–
50kΩ
15
WLDI
V
0
CONFIGURATION
REGISTER
SUPPLY
ARBITRATION
V
1
2
V
V
3
12
8
VDD_CAP
GND
CASCADE SEQUENCING
Time basedsequencinghastheabilitytoturnsupplieson
inaspecificorder. However,itcannotguaranteethateach
supply has reached valid voltage levels before the next
supplyissequencedon. Cascadesequencingguarantees
thesuppliesareenabledaprogrammedperiodoftimeafter
the previous voltage has reached its minimum pro-
grammedvalidlevel. Figure1showsthateachsucceeding
voltagemustreachitsminimumvalidlevelbeforethetimer
is started to time the interval, t, for the next voltage. The
duration of each t is programmable for each supply to
supply transition. The next supply is not enabled until the
timer has elapsed. See also Figure 5.
6V
4V
2V
0V
5V
5V Valid
3.3V Valid
3.3V
V
2.5V
1.8V
2.5V Valid
t
t
t
T
2047 Fig01
Figure 1. Cascading Power Supplies
SUMMIT MICROELECTRONICS, Inc.
2087 1.1 04/11/05
2
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
