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SMM150NR04 参数 Datasheet PDF下载

SMM150NR04图片预览
型号: SMM150NR04
PDF下载: 下载PDF文件 查看货源
内容描述: 单通道电源电压Marginer /监视器 [Single-Channel Supply Voltage Marginer/Monitor]
分类和应用: 监视器
文件页数/大小: 22 页 / 383 K
品牌: SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
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SMM150  
Preliminary Information  
PIN DESCRIPTIONS  
Ultra  
QFN  
CSPTM  
Ball  
Pin  
Pad  
Pin Name  
Pin Description  
Type  
Number  
Number  
SDA  
SCL  
A2  
I2C Bi-directional data line  
I2C clock input.  
28  
1
B2  
A1  
B1  
C1  
D1  
I/O  
I
I
I
I
The address pins are biased either to VDD, GND or left floating. This  
allows for a total of 21 distinct device addresses. When  
2
A1  
4
communicating with the SMM150 over the 2-wire bus these pins  
provide a mechanism for assigning a unique bus address.  
A0  
6
Programmable Write Protect active high/low input. When asserted,  
writes to the configuration registers and general purpose EE are not  
allowed. The WP input is internally tied to VDD with a 50Kresistor.  
WP  
8
D2  
I
External capacitor input used to filter the VM input, 0.2µF.  
10  
20  
E2  
B3  
CAP CAPM  
Output voltage used to control and/or margin converter voltages.  
Connect to the converter trim input.  
O
I
TRIM  
VM  
Voltage monitor input. Connect to the DC-DC converter positive sense  
line or its’ +Vout pin.  
14  
E4  
Power supply of the part.  
21  
23  
A4  
A3  
PWR VDD  
External capacitor input used to filter the internal VDD supply rail.  
PWR VDD_CAP  
Ground of the part. The SMM150 ground pin should be connected to  
the ground of the device under control or to a star point ground. PCB  
layout should take into consideration ground drops.  
7
E1  
C3  
GND GND  
Margin up command input. Asserted high. The MUP input is internally  
tied to VDD with a 50Kresistor.  
Margin down command input. Asserted high. The MDN input is  
internally tied to VDD with a 50Kresistor.  
24  
I
MUP  
25  
19  
A2  
B4  
I
I
MDN  
COMP1 and COMP2 are high impedance inputs, each connected  
internally to a comparator and compared against the internally  
programmable VREF voltage. Each comparator can be independently  
programmed to monitor for UV or OV. The monitor level is set  
externally with a resistive voltage divider.  
COMP1  
12  
11  
5
E3  
D3  
C2  
I
COMP2  
FAULT#  
READY  
When either of the COMP1 or COMP2 inputs are in fault the open-  
drain FAULT# output will be pulled low. A configuration option exists  
to disable the FAULT# output while the device is margining.  
O
Programmable active high/low open drain output indicates that VM is  
at its set point. When programmed as an active high output, READY  
can also be used as an input. When pulled low, it will latch the state of  
the comparator inputs.  
I/O  
3, 9, 13,  
15-18,  
22, 26,  
27, 29  
No Connect. The bottom side metal plate (Pad 29) can be connected  
to GND or left floating.  
C4, D4  
NC  
NC  
Summit Microelectronics, Inc  
2075 2.6 05/13/05  
4