SMM105
Preliminary Information
PIN DESCRIPTIONS
Ultra
QFN
CSPTM
Ball
Pin
Pad
Pin Name
SDA
SCL
A2
Pin Description
Type
Number
Number
28
1
2
4
6
A3
A1
A2
B2
C2
DATA
CLK
I2C Bi-directional data line
I2C clock input.
The address pins are biased either to VDD_CAP or GND. When
communicating with the SMM105 over the 2-wire bus these pins
provide a mechanism for assigning a unique bus address.
I
I
I
A1
A0
Write Protect active low input. When asserted, writes to the
8
E1
I
WP#
configuration registers and general purpose EE are not allowed.
10
18
E2
C5
CAP
CAP
FILT_CAP
TRIM_CAP
External capacitor input used to filter the VM input.
External capacitor input used for Active Control and margining.
Output voltage used to control and/or margin converter voltages.
20
14
B5
E4
O
I
TRIM
VM
Connect to the converter trim input.
Voltage monitor input. Connect to the DC-DC converter positive
sense line or its’ +Vout pin.
Voltage reference input used for DC output control and margining.
9
21
7
D2
B4
D1
I
VREF_CNTL VREF_CNTL can be programmed to output the internal 1.25V
reference. Pin should be left open if using VREF internal
PWR
GND
VDD
GND
Power supply of the part.
Ground of the part. The SMM105 ground pin should be connected
to the ground of the device under control or to a star point ground.
PCB layout should take into consideration ground drops.
12V power supply input internally regulated to either 3.6V or 5.5V.
When using the 3.6V internal regulator option, the 12VIN input can
be as low as 8V. It can be as high as 15V using the 5.5V internal
regulator.
Programmable active high/low input. The START input is used
solely for enabling Active Control and/or margining. There is also
a programmable start delay time, TSTART to delay ADOC/Margin
control.
22
3
A5
B1
C1
PWR
I
12VIN
START
READY
Programmable active high/low open drain output indicates that VM
is at its set point. When programmed as an active high output,
READY can also be used as an input. When pulled low, it will latch
the state of the comparator inputs.
5
I/O
23
19
A4
C4
CAP
I
VDD_CAP
COMP1
External capacitor input used to filter the internal supply rail.
COMP1 and COMP2 are high impedance inputs, each connected
internally to a comparator and compared against the VREF_CNTL
input. Each comparator can be independently programmed to
monitor for UV or OV. The monitor level is set externally with a
resistive voltage divider.
When either of the COMP1 or COMP2 inputs are in fault the open-
drain FAULT# output will be pulled low. A configuration option
exists to disable the FAULT# output while the device is margining.
12
11
E3
D3
I
COMP2
O
FAULT#
NC
B3,C3,
D4,D5,
E5
13,15,16
17,24-27
No Connect. Leave floating; do not connect anything to the NC
pins.
NC
Summit Microelectronics, Inc
2068 1.8 09/20/05
4
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
