SMM105
Preliminary Information
INTERNAL BLOCK DIAGRAM
VREF_CNTL
READY
FAULT#
MUX
VREF
V+
V-
COMP1
OV/UV
Output
Control
TRIM
Trim
Drive
TRIM_CAP
COMP2
OV/UV
START
W P#
I2C Serial
Interface
A0
A1
A2
SDA
SCL
Input Voltage
Sensing and
Signal
Conditioning
VM
3.6/5V
12VIN
EE
Regulator
Configuration
Registers
Supply
Arbitration
VDD
VDD_CAP
& Memory
Figure 3 – SMM105 Controller Internal Block Diagram.
PACKAGE AND PIN CONFIGURATION
25 Ball Ultra CSPTM
28 Pin QFN
Top View
Bottom View
Pin 1
Pin 1
SCL
A1
12VIN
A5
A2
VDD_CAP
SDA
A3
NC
23
22
28
26 25
27
24
A2
A4
1
21
20
19
SCL
A2
VDD
A1
VDD
TRIM
START
2
3
TRIM
COMP1
TRIM_CAP
NC
B5
B1
READY
C1
B2
A0
B3
B4
NC COMP1
START
A1
TRIM_CAP
C5
SMM105
4
5
6
7
18
17
16
15
READY
A0
C2
C3
C4
NC
NC
FAULT#
NC
GND VREF_CNTL
GND
NC
D5
NC
D1
D2
D3
D4
VM
13
14
9
10 11
8
12
WP# FILT_CAP COMP2
E5
E1
E2
E3
E4
Summit Microelectronics, Inc
2068 1.8 09/20/05
3
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
