W137
Pin Definitions
Pin
Type
Pin Name
Pin No.
Pin Description
CPU0:1
24, 23
O
O
O
I
CPU Clock Outputs 0 and 1. These two CPU clock outputs are controlled by the
CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ2. Frequency is selected per Table 1.
PCI1:±
±, 6, 9, 10, 11
PCI Bus Clock Outputs 1 through ±. These five PCI clock outputs are controlled by
the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ3. Frequency is selected per Table 1.
PCI_F
4
Fixed PCI Clock Output. Unlike PCI1:± outputs, this output is not controlled by the
PCI_STOP# control pin; it cannot be forced LOW by PCI_STOP#. Output voltage
swing is controlled by voltage applied to VDDQ3. Frequency is selected per Table 1.
CPU_STOP#
PCI_STOP#
REF0/SEL48#
18
20
27
CPU_STOP# Input. When brought LOW, clock outputs CPU0:1 are stopped LOW
after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH,
clock outputs CPU0:1 start with a full clock cycle (2–3 CPU clock latency).
I
PCI_STOP# Input. The PCI_STOP# input enables the PCI1:± outputs when HIGH
and causes them to remain at logic 0 when LOW. The PCI_STOP# signal is latched
on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle.
I/O I/O Dual-Function REF0 and SEL48# Pin. Upon power-up, the state of SEL48# is
latched. The state is set by either a 10K resistor to GND or to VDD. A 10K resistor to
GND causes pin 14 to provide a 48-MHz clock. If the pin is strapped to VDD, pin 14
will provide a 24-MHz clock. After 2 ms, the pin becomes a high-drive output that
produces a copy of 14.318 MHz.
REF1/SPREAD#
24/48MHz/OE
26
14
I/O I/O Dual-Function REF1 and SPREAD# Pin. Upon power-up, the state of SPREAD#
is latched. The state is set by either a 10K resistor to GND or to VDD. A 10K resistor
to GND enables Spread Spectrum function. If the pin is strapped to VDD, Spread
Spectrum is disabled. After 2 ms, the pin becomes a high-drive output that produces
a copy of 14.318 MHz.
I/O I/O Dual-Function 24 MHz or 48 MHz Output and Output Enable Input. Upon
power-up, the state of pin 14 is latched. The state is set by either a 10K resistor to
GND or to VDD. A 10K resistor to GND latches OE LOW, and all outputs are tri-stated.
If the pin is strapped to VDD, OE is latched HIGH and all outputs are active. After 2
ms, the pin becomes an output whose frequency is set by the state of pin 27 on
power-up.
48MHz
SEL100/66#
X1
13
16
2
O
48 MHz Output. Fixed 48 MHz USB output. Output voltage swing is controlled by
voltage applied to VDDQ3.
I
Frequency Selection Input. Select power-up default CPU clock frequency as shown
in Table 1.
I
Crystal Connection or External Reference Frequency Input. This pin can either be
used as a connection to a crystal or to a reference signal.
X2
3
I
Crystal Connection. An input connection for an external 14.318 MHz crystal. If using
an external reference, this pin must be left unconnected.
PWR_DWN#
17
I
Power Down Control. When this input is LOW, device goes into a low-power standby
condition. All outputs are held LOW. CPU and PCI clock outputs are stopped LOW
after completing a full clock cycle (2–3 CPU clock cycle latency). When brought
HIGH, CPU and PCI outputs start with a full clock cycle at full operating frequency
(3 ms maximum latency).
VDDQ3
VDDQ2
GND
8, 12, 19, 28
2±
P
P
G
Power Connection. Connected to 3.3V.
Power Connection. Power supply for CPU0:1 output buffers. Connected to 2.±V.
Ground Connection. Connect all ground pins to the common system ground plane.
1, 7, 1±, 21, 22
Rev 1.0,November 24, 2006
Page 2 of 8
SPECTRALINEAR [ SPECTRALINEAR INC ]
