SL15300
VIN=VDD, Pins 4 and 8. If
outputs are programmed as
PD#, OE, SSON# or FS and no
pull-up/down resister used
Input High Current
Input Low Current
IIH
IIL
-15
-15
-
-
15
15
μA
μA
VIN=GND, Pins 4 and 8. If
outputs are programmed as
PD#, OE, SSON# or FS and no
pull-up/down resister used
CMOS Level, if Pins 4 and 8
programmed as PD#, OE,
SSON# or FS
Pull-up or Down Resistors
Operating Supply Current
RPU/D
IDD
100
-
150
8.2
250
9.8
kΩ
FIN=30MHz and all 4 clocks are
mA
at 66MHz and +/-2.0% Spread
and CL=0
Standby Current
ISBC
IOL
PD#=GND
-
80
-
100
10
μA
μA
Pins 4, 6, 7 and 8. If
programmed as SSCLK or
REFCLK
Output Leakage Current
-10
Minimum setting value
Maximum setting value
Resolution (programming steps)
Pins 4 and 8
-
-
-
7
-
-
-
pF
pF
pF
Programmable
Input Capacitance at
Pins 2 and 3
PCin
38
0.5
PCout
Input Capacitance
Load Capacitance
CIN2
CL
-
-
4
-
6
pF
pF
If programmed as PD#, OE,
SSON or FS
Pins 4, 6, 7 and 8. If
programmed as SSCLK or
REFCLK
15
AC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C
Parameter
Symbol
FIN1
Condition
Crystal or Ceramic Resonator
External Clock
Min
8
Typ
Max
48
Unit
MHz
MHz
MHz
MHz
MHz
%
Input Frequency Range
Input Frequency Range
Output Frequency Range
Output Frequency Range
Output Frequency Range
Output Duty Cycle
-
-
FIN2
3
166
200
48
FOUT1 SSCLK
3
-
FOUT2 REFCLK, crystal or resonator input
FOUT3 REFCLK, clock input
0.25
0.25
45
-
-
166
55
DC1
DC2
DC3
DCIN
tr/f1
SSCLK
50
50
50
50
Output Duty Cycle
REFCLK, Xtal input
REFCLK, clock input
Clock Input, Pin 3
45
55
%
Output Duty Cycle
40
60
%
Input Duty Cycle
40
60
%
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
Output Rise/Fall Time
-
4.00
4.80
ns
Rev 1.0, August 14, 2008
Page 9 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
