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SL15300ZC-XXX 参数 Datasheet PDF下载

SL15300ZC-XXX图片预览
型号: SL15300ZC-XXX
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程扩频时钟发生器( SSCG ) [Programmable Spread Spectrum Clock Generator (SSCG)]
分类和应用: 时钟发生器
文件页数/大小: 16 页 / 368 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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SL15300  
FIN=30MHz and all 4 clocks are  
Operating Supply Current  
IDD  
-
7.9  
9.4  
mA  
at 66MHz and +/-2.0% Spread  
and CL=0  
Standby Current  
ISBC  
IOL  
PD#=GND  
-
70  
-
90  
10  
μA  
μA  
Pins 4, 6, 7 and 8 if  
programmed as SSCLK or  
REFOUT  
Output Leakage Current  
-10  
Minimum setting value  
-
-
-
7
-
-
-
pF  
pF  
pF  
Programmable  
Input Capacitance at  
Pins 2 and 3  
PCin  
Maximum setting value  
38  
0.5  
PCout  
Resolution (programming steps)  
Pins 4 and 8 if programmed as  
PD#, OE, SSON or FS  
Input Capacitance  
Load Capacitance  
CIN2  
CL  
-
-
4
-
6
pF  
pF  
Pins 4, 6, 7 and 8 If  
programmed as SSCLK or  
REFCLK  
15  
AC Electrical Characteristics (C-Grade)  
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70 Deg C  
Parameter  
Symbol  
FIN1  
Condition  
Crystal or Ceramic Resonator  
External Clock  
Min  
8
Typ  
Max  
48  
Unit  
MHz  
MHz  
MHz  
MHz  
MHz  
%
Input Frequency Range  
Input Frequency Range  
Output Frequency Range  
Output Frequency Range  
Output Frequency Range  
Output Duty Cycle  
-
-
FIN2  
3
166  
200  
48  
FOUT1 SSCLK  
3
-
FOUT2 REFCLK, crystal or resonator input  
FOUT3 REFCLK, clock input  
0.25  
0.25  
45  
-
-
166  
55  
DC1  
DC2  
DC3  
DCIN  
tr/f1  
SSCLK  
50  
50  
50  
50  
Output Duty Cycle  
REFCLK , Xtal input  
REFCLK, clock input  
Clock Input, Pin 3  
45  
55  
%
Output Duty Cycle  
40  
60  
%
Input Duty Cycle  
40  
60  
%
Programmable, VDD=3.3V,  
CL=15pF, 20 to 80% of VDD  
Output Rise/Fall Time  
Output Rise/Fall Time  
Output Rise/Fall Time  
Output Rise/Fall Time  
Output Rise/Fall Time  
Output Rise/Fall Time  
Output Rise/Fall Time  
-
-
-
-
-
-
-
4.00  
2.00  
1.40  
1.10  
0.85  
0.70  
0.55  
4.80  
2.40  
1.70  
1.35  
1.00  
0.85  
0.67  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tr/f2  
tr/f3  
tr/f4  
tr/f5  
tr/f6  
tr/f7  
Programmable, VDD=3.3V,  
CL=15pF, 20 to 80% of VDD  
Programmable, VDD=3.3V,  
CL=15pF, 20 to 80% of VDD  
Programmable, VDD=3.3V,  
CL=15pF, 20 to 80% of VDD  
Programmable, VDD=3.3V,  
CL=15pF, 20 to 80% of VDD  
Programmable, VDD=3.3V,  
CL=15pF, 20 to 80% of VDD  
Programmable, VDD=3.3V,  
CL=15pF, 20 to 80% of VDD  
Rev 1.0, August 14, 2008  
Page 5 of 16