SL15316
CL=15pF, 20 to 80% of VDD
tr/f6
tr/f7
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
-
-
-
0.65
0.50
TBD
-
-
ns
ns
ps
Output Rise/Fall Time
Programmable, VDD=3.3V,
CL=15pF, 20 to 80% of VDD
Output Rise/Fall Time
Cycle-to-Cycle Jitter
CCJ1
FIN=25MHz Clock, all 5 clocks are
at 66MHz, +/-1.0% Spread.
TBD
CL=10pF, VDD=VDDO1/2=3.3V
CCJ2
FIN=25MHz Clock, all 5 clocks are
at 166MHz, +/-1.0% Spread.
-
TBD
TBD
ps
Cycle-to-Cycle Jitter
CL=10pF, VDD=VDDO1/2=3.3V
tPD
tPU
Time from PD# falling edge to Hi-Z
at outputs (Asynchronous)
-
-
150
3.5
350
5.0
ns
Power-down Time
Time from PD# rising edge to valid
frequency at outputs
(Asynchronous)
ms
Power-up Time
(Crystal or Clock)
tOE
tOD
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
-
-
180
450
450
ns
ns
%
%
Output Enable Time
Output Disable Time
Spread Percent Range
Spread Percent Range
Time from OE falling edge to Hi-Z at
outputs (Asynchronous)
180
SPR-1
SPR-2
Center Spread, all programmed
SSCLKs
+/-0.125
-5.0
-
-
+/-2.5
-0.25
Down Spread, all programmed
SSCLKs
ΔSS%
FMOD
tPSR
Variation of programmed Spread %
Programmable, 31.5 kHz standard
-20
25
-
-
31.5
-
20
120
12
%
Spread Percent Variation
Modulation Frequency
kHz
ms
Time for VDD reaching minimum
specified value and monolithic
power supply ramp
Power Supply Ramp
Time
Rev 1.0, August 7, 2008
Page 9 of 12
SPECTRALINEAR [ SPECTRALINEAR INC ]
