W305B
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeat
CPU 133-MHz
SDRAM 133MHz
3V66 66-MHz
PCI 33-MHz
APIC 16.6-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 5. Group Offset Waveform (133-MHz CPU/133-MHz SDRAM)
Serial Data Interface
controller. For block write/read operation, the bytes must be
accessed in sequential order from lowest to highest byte with
the ability to stop after any complete byte has been trans-
ferred. For byte/word write and byte read operations, system
controller can access individual indexed byte. The offset of the
indexed byte is encoded in the command code.
The W305B features a two-pin, serial data interface that can
be used to configure internal register settings that control
particular device functions.
Data Protocol
The definition for the command code is given in Table 1.
The clock driver serial protocol supports byte/word write,
byte/word read, block write and block read operations from the
Table 1. Command Code Definition
Bit
Descriptions
7
0 = Block read or block write operation
1 = Byte/Word read or byte/word write operation
6:0
Byte offset for byte/word read or write operation. For block read or write operations, these bits
need to be set at ‘0000000’.
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
2:8
9
Slave address – 7 bit
Write
2:8
9
Slave address – 7 bit
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bit
‘00000000’ stands for block operation
11:18
Command Code – 8 bit
‘00000000’ stands for block operation
19
20:27
28
Acknowledge from slave
Byte Count – 8 bits
19
20
Acknowledge from slave
Repeat start
Acknowledge from slave
Data byte 0 – 8 bits
21:27
28
Slave address – 7 bits
Read
29:36
37
Acknowledge from slave
Data byte 1 – 8 bits
29
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
38:45
46
30:37
38
Acknowledge from slave
Data Byte N/Slave Acknowledge...
...
39:46
Data byte from slave – 8 bits
Rev 1.0,November 20, 2006
Page 5 of 20