W305B
Output Strapping Resistor
Series Termination Resistor
Clock Load
W305B
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
10 k:
Q
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below
target but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be
produced from the CPU clock outputs when the outputs are
enabled.
Overview
The W305B is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel® archi-
tecture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
Offsets Among Clock Signal Groups
Upon power-up the power on strap option pins act as a logic
input. An external 10-k: strapping resistor should be used.
Figure 1 shows a suggested method for strapping resistor
connections.
Figure 2, Figure 3, and Figure 4 represent the phase
relationship among the different groups of clock outputs from
W305B under different frequency modes.
10 ns
20 ns
30 ns
40 ns
0 ns
CPU 66 Period
CPU 66-MHz
SDRAM 100 Period
SDRAM 100-MHz
Hub-PCI
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 16.6-MHz
Figure 2. Group Offset Waveforms (66-MHz CPU Clock, 100-MHz SDRAM Clock)
Rev 1.0,November 20, 2006
Page 3 of 20
SPECTRALINEAR [ SPECTRALINEAR INC ]
