CY2SSTV16859
Pin Configuration (continued)
53
56 55
52
49 48 47
51 50
54
46 45 44 43
42
D10
Q7A
Q6A
Q5A
Q4A
1
D9
D8
D7
41
40
2
3
39
4
RESET#
Q3A
38
37
5
6
GND
CLK#
CLK
Q2A
Q1A
36
35
34
33
32
31
7
8
Q13B
9
VDDQ
VDD
VDDQ
Q12B
Q11B
10
11
12
VREF
Q10B
D6
13
14
30
29
Q9B
Q8B
D5
D4
18
15 16
19
22 23 24
20 21
25 26 27 28
17
56 QFN Package
Pin Description
Pin
Name
Description
TSSOP
QFN
51
38
RESET# Disable Clocking and Reset Latch
7,15,34,39,43,50,54,58,63
37,46,60
37,48
GND
VDD
Ground
26,33,45
Supply Voltage
Supply Voltage, Quiet
6,18,27,33,38,47,59,64
45
9,17,23,27,34,44,49,55
32
VDDQ
VREF
Reference Voltage for Data Inputs
D(1:13)
16,14,13,12,11,10,9,8,5,4,3,2,1
7,6,5,4,3,2,1,56,54,53,52,51,50
QA(1:13) Data Outputs
QB(1:13) Data Outputs
32,31,30,29,28,25,24,23,22,21,20, 22,21,20,19,18,16,15,14,13,12
19,17 11,10,8
35,36,40,41,42,44,52,53,55,56,57, 24,25,28,29,30,31,39,40,41,42
43,46,47
D(1:13)
Data Inputs
61,62
48,49
35,36
CLK, CLK# Differential Clock Signals
Table 1. Function Table[1,2,3]
INPUTS
OUTPUT
RESET#
CLK
CLK#
D
Q
L
H
H
H
L
n
n
p
p
L
H
X
H
L or H
X or floating
L or H
X or floating
Q0
L
X or floating
Notes:
1. H = High voltage level.
2. L = Low voltage level.
3. X = Don’t care.
Rev 1.0,November 21, 2006
Page 2 of 7
SPECTRALINEAR [ SPECTRALINEAR INC ]
