CY2SSTV16857
Table 1. DC Electrical Specifications (VDD = Temperature = 0°C to +85 °C) (continued)
Parameter
Description
Output Voltage, High
Condition
Min.
Typ.
Max. Unit
VOH
VDD/VDDQ = 2.3V to 2.7V, IOH
–100ꢀPA, VDD=2.3 to 2.7V
=
VDD
0.2
–
V
VDD/VDDQ = 2.3V, IOH = –16 mA
1.95
IIL
Input Current
Data Inputs
VI = 1.7V or 0.8V, VREF = 1.15V or
1.35V, VDD = 2.7V
5
PA
PA
PA
VI = 2.7V or 0,VREF = 1.15V or
1.35V, VDD = 2.7V
5
VI = 1.7V or 0.8V, VREF = 1.15V or
1.35V, VDD = 3.6V
5
5
VI = 2.7V or 0
PA
PA
CLK, CLK
VI = 1.7V or 0.8V, VREF = 1.15V or
1.35V
1
VI = 2.7V or 0, VREF = 1.15V or
1.35V, Vdd = 2.7V
1
5
PA
RESET
VI = VDD or VSS, VDD = 2.7V
VI = 1.5V or 1.35V, VDD = 2.7
Data inputs only
PA
PA
VREF
5
IIH
Input Current, High
Dynamic Supply Current
mA.
mA
IDD
VI = 1.7V or 0.8V, IO = 0, VDD
2.7V
=
90
90
VI = 2.7V or 0, IO = 0, VDD = 2.7V
mA
pF
Cin
Input pin capacitance
RESET
VI = 1.7V or 0.8V, IO = 0, VDD
2.7V
=
3
Clock and Data Inputs
Pin Inductance
2.5
2.1
2.7
3.5
4.5
pF
nH
Lpin
All
Table 2. AC Input Electrical Specifications (VDD = 2.5 VDC 5ꢀ, Temperature = 0°C to +85°C)
VDD = 2.5V 0.2V
Parameter
FIN
Description
Input Clock Frequency
Pulse Duration
Condition
Min.
Max.
Unit
MHz
ns
CLK, CLK
CLK, CLK HIGH or LOW
200
PW
3.3
22
22
TACT
Differential Inputs Active Time Data inputs must be LOW after RESET HIGH
ns
TINACT
Differential Inputs Inactive Time Data and clock inputs must be held at valid levels (not
floating) after RESET LOW
ns
TSET
Set-up Time
Fast slew rate, (see notes 5 and 7), Data before CLK,
CLK
0.75
0.9
ns
ns
Slow slew rate, (see notes 6 and 7), Data before CLK,
CLK
THOLD
Hold Time
Fast slew rate, (see notes 5 and 7), Data after CLK, CLK 0.75
ns
ns
Slow slew rate (see notes 6 and 7), Data after CLK, CLK
0.9
IVpp
Input Voltage, Pk–Pk
360
mV
Notes:
5. For data signal input slew rate > 1 V/ns.
6. For data signal input slew rate > 0.5 V/ns and < 1 V/ns.
7. CLK, CLK signals input slew rates are > 1 V/ns.
Rev 1.0,November 21, 2006
Page 4 of 7
SPECTRALINEAR [ SPECTRALINEAR INC ]
