CY28RS480
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
CPUT/C
SRCT/C
Spread Spectrum Selection
‘0’ = –0.35%
‘1’ = –0.50%
6
5
1
1
USB_48
PCI
48-MHz Output Drive Strength
0 = 2x, 1 = 1x
33-MHz Output Drive Strength
0 = 2x, 1 = 1x
4
3
2
0
1
0
Reserved
Reserved
Reserved
Reserved
CPU
SRC
CPU/SRC Spread Spectrum Enable
0 = Spread off, 1 = Spread on
1
0
1
1
Reserved
Reserved
Reserved
Reserved
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
1
CLKREQ#
CLKREQ# drive mode
0 = SRC clocks driven when stopped, 1 = SRC clocks tri-state when
stopped
6
5
0
1
CPU
SRC
CPU pd drive mode
0 = CPU clocks driven when power-down, 1 = CPU clocks tri-state
SRC pd drive mode
0 = SRC clocks driven when power-down, 1 = SRC clocks tri-state
4
3
2
1
0
0
1
1
1
1
Reserved
Reserved
Reserved
Reserved
HTT66
Reserved
Reserved
Reserved
Reserved
HTT66 Output Drive Strength0 = High drive, 1 = Low drive.
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
0
SRC[T/C]5
SRC[T/C]5 CLKREQ0 control
1 = SRC[T/C]5 stoppable by CLKREQ#0 pin
0 = SRC[T/C]5 free running
6
5
4
3
2
1
0
0
0
0
0
1
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
SRC[T/C]0
HTT66
SRC[T/C]4 CLKREQ#0 control
1 = SRC[T/C]4 stoppable by CLKREQ#0 pin
0 = SRC[T/C]4 free running
SRC[T/C]3 CLKREQ#0 control
1 = SRC[T/C]3 stoppable by CLKREQ#0 pin
0 = SRC[T/C]3 free running
SRC[T/C]2 CLKREQ#0 control
1 = SRC[T/C]2 stoppable by CLKREQ#0 pin
0 = SRC[T/C]2 free running
SRC[T/C]1 CLKREQ#0 control
1 = SRC[T/C]1 stoppable by CLKREQ#0 pin
0 = SRC[T/C]1 free running
SRC[T/C]0 CLKREQ#0 control
1 = SRC[T/C]1 stoppable by CLKREQ#0 pin
0 = SRC[T/C]1 free running
HTT66 Output enable
0 = Disabled, 1 = Enabled
Rev 1.0,November 22, 2006
Page 5 of 14
SPECTRALINEAR [ SPECTRALINEAR INC ]
