CY28RS480
Serial Data Interface
Data Protocol
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 1. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:5)
(4:0)
Chip select address, set to ‘00’ to access device
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address – 7 bits
Write
8:2
9
Slave address – 7 bits
Write
10
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N – 8 bits
Acknowledge from slave
Stop
10
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeat start
18:11
19
18:11
19
27:20
28
20
27:21
28
Slave address – 7 bits
Read = 1
36:29
37
29
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
45:38
46
37:30
38
....
46:39
47
Data byte 1 from slave – 8 bits
Acknowledge
....
....
55:48
56
Data byte 2 from slave – 8 bits
Acknowledge
....
....
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
....
....
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address – 7 bits
Write
8:2
9
Slave address – 7 bits
Write
10
Acknowledge from slave
10
Acknowledge from slave
Rev 1.0,November 22, 2006
Page 3 of 14
SPECTRALINEAR [ SPECTRALINEAR INC ]
