CY28RS480
Byte 4: Control Register 4 (continued)
Bit
@Pup
Name
Description
Description
0
1
Reserved
Reserved
Byte 5: Control Register 5
Bit
@Pup
Name
7
0
SRC[T/C]5
SRC[T/C]5 CLKREQ#1 control
1 = SRC[T/C]5 stoppable by CLKREQ#1 pin
0 = SRC[T/C]5 free running
6
5
4
3
2
0
0
0
0
0
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
SRC[T/C]0
SRC[T/C]4 CLKREQ#1 control
1 = SRC[T/C]4 stoppable by CLKREQ#1 pin
0 = SRC[T/C]4 free running
SRC[T/C]3 CLKREQ#1 control
1 = SRC[T/C]3 stoppable by CLKREQ#1 pin
0 = SRC[T/C]3 free running
SRC[T/C]2 CLKREQ#1 control
1 = SRC[T/C]2 stoppable by CLKREQ#1 pin
0 = SRC[T/C]2 free running
SRC[T/C]1 CLKREQ#1 control
1 = SRC[T/C]1 stoppable by CLKREQ#1 pin
0 = SRC[T/C]1 free running
SRC[T/C]0 CLKREQ#1 control
1 = SRC[T/C]1 stoppable by CLKREQ#1 pin
0 = SRC[T/C]1 free running
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
TEST_SEL
REF/N or Three-state Select
1 = REF/N Clock, 0 = Three-state
6
5
0
0
TEST_MODE
REF
Test Clock Mode Entry Control
1 = REF/N or Tri-state mode, 0 = Normal operation
REF Output drive strength
0 = Low drive, 1 = High drive
4
3
2
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
HW
HW
HW
HW
Byte 7: Vendor ID
Bit
7
@Pup
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
0
0
0
1
1
0
0
0
6
5
4
3
2
Vendor ID Bit 2
1
Vendor ID Bit 1
0
Vendor ID Bit 0
Rev 1.0,November 22, 2006
Page 6 of 14
SPECTRALINEAR [ SPECTRALINEAR INC ]
