CY28RS480
Table 3. Byte Read and Byte Write Protocol (continued)
Byte Write Protocol
Byte Read Protocol
Description
Command Code – 8 bits
Bit
18:11
19
Description
Command Code – 8 bits
Bit
18:11
19
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Acknowledge from slave
Repeated start
27:20
28
20
27:21
28
Slave address – 7 bits
Read
29
29
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
37:30
38
39
Control Registers
Byte 0:Control Register 0
Bit
@Pup
Name
Description
7
1
SRC[T/C]5
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
6
5
4
3
2
1
0
1
1
1
1
1
1
1
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
SRC [T/C]0
SRCS[T/C]1
SRCS[T/C]0
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRCS[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRCS[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
1
REF2
REF2 Output Enable
0 = Disable, 1 = Enable
6
5
4
3
1
1
1
1
REF1
REF0
REF1 Output Enable
0 = Disable, 1 = Enable
REF0 Output Enable
0 = Disable, 1 = Enable
PCI0
PCI0 Output Enable
0 = Disable, 1 = Enable
USB_48
USB_48MHz Output Enable
0 = Disable, 1 = Enable
2
1
1
1
RESERVED
CPU[T/C]1
RESERVED
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
0
1
CPU[T/C]0
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Rev 1.0,November 22, 2006
Page 4 of 14
SPECTRALINEAR [ SPECTRALINEAR INC ]
