CY28443-3
Byte 3: Control Register 3
Bit
7
@Pup
Name
RESERVED
RESERVED
SRC5
Description
0
0
0
RESERVED, Set = 0
RESERVED, Set = 0
6
5
Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
4
3
2
0
0
0
SRC4
SRC3
SRC2
Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
1
0
0
0
RESERVED
SRC0
RESERVED, Set = 0
Allow control of SRC[T/C]0 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
0
100M[T/C]_SST
100M[T/C]_SST PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
6
5
4
3
2
1
0
0
1
0
0
1
1
1
DOT96[T/C]
SRC[T/C]
PCIF1
DOT PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
SRC[T/C] Stop Drive Mode when CLKREQ# asserted
0 = Driven, 1 = Tri-state
Allow control of PCIF1 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
PCIF0
Allow control of PCIF0 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
SRC[T/C]
SRC[T/C] Stop Drive Mode
0 = Driven when PCI_STP# asserted, 1 = Tri-state when PCI_STP#
asserted
6
5
4
0
0
0
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#
asserted
CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#
asserted
CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#
asserted
3
2
0
0
SRC[T/C]
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted, 1 = Tri-state when PD asserted
CPU[T/C]2
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted, 1 = Tri-state when PD asserted
Rev 1.0,November 20, 2006
Page 6 of 23
SPECTRALINEAR [ SPECTRALINEAR INC ]
