CY28443-3
Pin Descriptions
Pin No.
Name
Type
Description
1, 7, 11, 21, VDD
28, 34, 42, 48
PWR 3.3V power supply.
2, 6, 13, 29, VSS
45, 51
GND Ground.
3,4
5
PCI[3:4]
PCI5/FCTSEL1
O, SE 33-MHz clock.
O, SE 33-MHz clock/3.3 LVTTL input for selecting for pin 14, 15 (DOT96[T/C],
PD 27M-non-spread and Spread) and pin 17,18 (SRC[T/C]0 or 100M[T/C]_SST)
(sampled on the VTT_PWRGD# assertion).
FCTSEL1 FCTSEL0 PIN 14
PIN 15
PIN 17
PIN 18
0
0
1
1
0
1
0
1
DOT96T
DOT96T
DOT96C
DOT96C
100MT_SST 100MC_SST
SRCT0
SRCC0
SRCC0
SRCC0
27M_non spread 27M_Spread SRCT0
OFF Low TBD SRCT0
8
ITP_SEL/PCIF0
I/O, SE 3.3V LVTTL input to enable SRC[T/C]11or CPU[T/C]2_ITP/33-MHz clock
output. (sampled on the VTT_PWRGD# assertion).
1 = CPU_ITP, 0 = SRC11
9
PCIF1
I/O, SE 33-MHz clock.
10
VTT_PWRGD#/PD
I, PU 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS[C:A],
ITP_SEL, FCTSEL[1:0], SEL_CLKREQ#. After VTT_PWRGD# (active LOW)
assertion, this pin becomes a real-time input for asserting power-down (active
HIGH).
12
FSA/48M
I/O
3.3V-tolerant input for CPU frequency selection/Fixed 48-MHz clock output.
Refer to DC Electrical Specification Table for Vil_FS and Vih_FS specifications.
14, 15
DOT96T/27M_non
spread
DOT96C/27M_Spread
O, DIF Fixed 96-MHz Differential Clock/ Single ended 27-MHz clocks. When
configured for 27-MHz, only the clock on pin 15 contains spread. Selected via
FCTSEL[0:1] at VTT_PWRGD# assertion.
16
FSB
I
3.3V-tolerant input for CPU frequency selection.
Refer to DC Electrical Specification Table for Vil_FS and Vih_FS specifications
17,18
SRC[T/C]0/
100M[T/C]_SST
O,DIF 100-MHz Differential Serial Reference Clock/ 100-MHz LVDS Differential
Clock.
19,20,22,23, SRC[T/C]
24,25,30,31
O, DIF 100-MHz Differential Serial Reference Clocks.
26,27
33,32
SRC[T/C]5_SATA
O, DIF Differential serial reference clock. Recommended output for SATA.
SRCT9/CLKREQ#A, I/O, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW) / 100-MHz
SRCC9/CLKREQ#B
Serial Reference Clock.
Default function is CLKREQ#
36,35
CPUT2_ITP/SRCT11, O, DIF Selectable differential CPU / SRC clock output.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC11,
ITP_EN = 1@ VTT_PWRGD# assertion =CPU2_ITP
CPUC2_ITP/SRCC11
37
38
39
VDDA
VSSA
IREF
PWR 3.3V power supply for PLL.
GND Ground for PLL.
I
A precision resistor is attached to this pin, which is connected to the internal
current reference.
44,43,41,40 CPU[T/C][0:1]
O, DIF Differential CPU clock outputs.
46
47
SCLK
I
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
SDATA
I/O
OD
49
50
XOUT
XIN
O, SE 14.318-MHz crystal output.
14.318-MHz crystal input.
I
Rev 1.0,November 20, 2006
Page 2 of 23
SPECTRALINEAR [ SPECTRALINEAR INC ]
