CY28442
Pin Definitions
Pin No.
Name
VDD_REF
VSS_REF
Type
Description
1
PWR 3.3V power supply for outputs.
GND Ground for outputs.
2
33,32
CLKREQA#/SRCT6, I/O, PU 3.3V LVTTL input for enabling assigned SRC clock (active low) or 100 MHz
CLKREQB#,SRCC6
Serial Reference Clock.
Selectable through
CLKREQA# defaults to enable/disable SRCT/C4, CLKREQB# defaults to
enable/disable SRCT/C5. Assignment can be changed via SMBUS register Byte
8.
7
VDD_PCI
VSS_PCI
PCI
PWR 3.3V power supply for outputs.
GND Ground for outputs.
O, SE 33-MHz clock
6
3,4,5
8
ITP_EN/PCIF0
I/O, SE 3.3V LVTTL input to enable SRC7 or CPU2_ITP/33 MHz clock output.
(sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC7
9
PCIF1/96_100_SEL
VTT_PWRGD#/PD
I/O, 33-MHz clock/3.3V-tolerant input for 96_100M frequency selection
PD,SE (sampled on the VTT_PWRGD# assertion).
1 = 100MHz, 0 = 96MHz
10
I, PU 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, and ITP_EN, 96MSS_SRC_SEL inputs, SEL_CLKREQ. After
VTT_PWRGD# (active low) assertion, this pin becomes a real-time input for
asserting power down (active high).
11
12
VDD_48
PWR 3.3V power supply for outputs.
FS_A/48_M0
I/O
3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
13
VSS_48
GND Ground for outputs.
14,15
16
DOT96T, DOT96C
FS_B/TEST_MODE
O, DIF Fixed 96-MHz clock output.
I
3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state
when in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
17,18
96_100_SSC
O,DIF Differential 96/100 MHz SS clock for flat-panel display
O, DIF 100 MHz Differential serial reference clocks.
19,20,22,23, SRCT/C
24,25,30,31
21,28
34
VDD_SRC
PWR 3.3V power supply for outputs.
VDD_SRC_ITP
PWR 3.3V power supply for outputs.
26,27
SRC4_SATAT,
SRC4_SATAC
O, DIF Differential serial reference clock. Recommended output for SATA.
29
VSS_SRC
GND Ground for outputs.
36,35
CPUT2_ITP/SRCT7, O, DIF Selectable differential CPU or SRC clock output.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
CPUC2_ITP/SRCC7
37
38
39
VDDA
VSSA
IREF
PWR 3.3V power supply for PLL.
GND Ground for PLL.
I
A precision resistor is attached to this pin, which is connected to the internal
current reference.
42
VDD_CPU
PWR 3.3V power supply for outputs.
O, DIF Differential CPU clock outputs.
GND Ground for outputs.
44,43,41,40 CPUT/C
45
46
47
VSS_CPU
SCLK
I
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
SDATA
I/O
Rev 1.0,November 21, 2006
Page 2 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
