CY28442
Byte 5: Control Register 5 (continued)
Bit
@Pup
Name
Description
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
1
0
CPU[T/C]1
0
0
CPU[T/C]0
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
TEST_SEL
REF/N or Tri-state Select
0 = Tri-state, 1 = REF/N Clock
6
0
TEST_MODE
Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Tri-state mode,
5
4
0
1
RESERVED
REF
RESERVED
REF Output Drive Strength
0 = Low, 1 = High
3
1
PCI, PCIF and SRC clock SW PCI_STP Function
outputs except those set 0=SW PCI_STP assert, 1= SW PCI_STP deassert
to free running
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
2
1
0
HW
HW
HW
FS_C
FS_B
FS_A
FS_C Reflects the value of the FS_C pin sampled on power up
0 = FS_C was low during VTT_PWRGD# assertion
FS_B Reflects the value of the FS_B pin sampled on power up
0 = FS_B was low during VTT_PWRGD# assertion
FS_A Reflects the value of the FS_A pin sampled on power up
0 = FS_A was low during VTT_PWRGD# assertion
Byte 7: Vendor ID
Bit @Pup
Name
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
7
6
5
4
3
2
1
0
0
0
0
0
1
0
0
0
Vendor ID Bit 2
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 1
Vendor ID Bit 0
Vendor ID Bit 0
Byte 8: Control Register 8
Bit
@Pup
Name
Description
7
6
5
4
0
CLKREQ#B
SRC[T/C]7CLKREQ#B control
1 = SRC[T/C]7 stoppable by CLKREQ#B pin
0 = SRC[T/C]7 not controlled by CLKREQ#B pin
1
0
0
CLKREQ#B
CLKREQ#B
CLKREQ#B
SRC[T/C]5 CLKREQ#B control
1 = SRC[T/C]5 stoppable by CLKREQ#B pin
0 = SRC[T/C]5 not controlled by CLKREQ#B pin
SRC[T/C]3 CLKREQ#B control
1 = SRC[T/C]3 stoppable by CLKREQ#B pin
0 = SRC[T/C]3 not controlled by CLKREQ#B pin
SRC[T/C]1 CLKREQ#B control
1 = SRC[T/C]1 stoppable by CLKREQ#B pin
0 = SRC[T/C]1 not controlled by CLKREQ#B pin
Rev 1.0,November 21, 2006
Page 7 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
