CY28419
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF
Figure 3. Power-down Assertion Timing Waveforms
PD# Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 1.8 ms. The
CPUT/C outputs must be driven to greater than 200 mV is less
than 300 us.
Tstable
<1.8ms
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF
Tdrive_PWRDN#
<300PS, >200mV
Figure 4. Power-down Deassertion Timing Waveforms
Rev 1.0,November 22, 2006
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