CY28416
Tstable
<1.8 ms
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33MHz
REF
Tdrive_PWRDN#
<300PS, >200mV
Figure 4. Power-down Deassertion Timing Waveform
FS_A, FS_B,FS_C
VTT_PWRGD#
PWRGD_VRM
0.2-0.3mS
Delay
Wait for
VTT_PWRGD#
Device is not affected,
VTT_PWRGD# is ignored
Sample Sels
State 2
VDD Clock Gen
Clock State
State 0
Off
State 1
State 3
On
Clock Outputs
Clock VCO
On
Off
Figure 5. VTT_PWRGD# Timing Diagram
S2
S1
VTT_PW RGD# = Low
Sample
Inputs straps
Delay >0.25 ms
VDD_A = 2.0V
W ait for <1.8ms
S0
S3
VDD_A = off
Normal
Operation
Enable Outputs
Power Off
VTT_PW RGD# = toggle
Figure 6. Clock Generator Power-up/Run State Diagram
Rev 1.0,November 22, 2006
Page 9 of 14
SPECTRALINEAR [ SPECTRALINEAR INC ]
