CY28416
Byte 1: Control Register 1
Bit
7
@Pup
Name
Description
1
1
Spread Selection
DOT_96T/C
0=Center Spread, 1= Down Spread (Default)
6
DOT_96 MHz Output Enable
0 = Disable (Hi-Z), 1 = Enabled
5
4
3
2
1
0
1
1
1
1
1
0
48 MHz0, 48 MHz1
REF0
48-MHz Output Enable
0 = Disabled, 1 = Enabled
REF Output Enable
0 = Disabled, 1 = Enabled
REF1
REF Output Enable
0 = Disabled, 1 = Enabled
CPU[T/C]1
CPU[T/C]0
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
CPUT/C
SRCT/C
PCIF
Spread Spectrum Enable
0 = Spread off, 1 = Spread on
PCI
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
PCI3
PCI3 Output Enable
0 = Disabled, 1 = Enabled
6
1
PCI2
PCI2 Output Enable
0 = Disabled, 1 = Enabled
5
4
3
1
1
1
RESERVED
RESERVED
PCI1
RESERVED, Set = 1
RESERVED, Set = 1
PCI1 Output Enable
0 = Disabled, 1 = Enabled
2
1
0
1
1
1
PCI0
PCIF1
PCIF0
PCI0 Output Enable
0 = Disabled, 1 = Enabled
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
0
SRC[T/C]4
Allow control of SRC[T/C]4 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
6
5
4
0
0
0
RESERVED
RESERVED
SRC[T/C]3
RESERVED, Set = 0
RESERVED, Set = 0
Allow control of SRC[T/C]3 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
3
2
1
0
0
0
0
0
SRC2_SATA
SRC[T/C]1
SRC[T/C]0
RESERVED
Allow control of SRC2_SATA with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
RESERVED, Set = 0
Rev 1.0,November 22, 2006
Page 5 of 14
SPECTRALINEAR [ SPECTRALINEAR INC ]
