CY28411-1
Byte 3: Control Register 3 (continued)
Bit
@Pup
Name
Description
4
0
SRC4
Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
3
2
1
0
0
0
0
0
SRC3
SRC2
SRC1
SRC0
Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]0 with assertion of PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Byte 4: Control Register 4
Bit
7
@Pup
Name
Description
0
0
Reserved
DOT96T/C
Reserved, Set = 0
6
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Hi-Z
5
4
0
0
Reserved
PCIF1
Reserved, Set = 0
Allow control of PCIF1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
3
2
1
0
0
1
1
1
PCIF0
Allow control of PCIF0 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
SRC[T/C][7:0]
SRC[T/C] Stop Drive Mode
0 = Driven when PCI_STP# asserted,1 = Hi-Z when PCI_STP# asserted
6
5
4
3
2
1
0
0
0
0
0
0
0
0
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
SRC[T/C][7:0]
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted
CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted
CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
Rev 1.0,November 22, 2006
Page 6 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
