CY28411-1
Table 3. Block Read and Block Write Protocol (continued)
Block Write Protocol
Block Read Protocol
Description
Slave address – 7 bits
Bit
28
Description
Acknowledge from slave
Bit
27:21
28
36:29
37
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N –8 bits
Acknowledge from slave
Stop
Read = 1
29
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
45:38
46
37:30
38
....
46:39
47
Data byte 1 from slave – 8 bits
Acknowledge
....
....
55:48
56
Data byte 2 from slave – 8 bits
Acknowledge
....
....
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
....
....
....
Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address – 7 bits
Write
8:2
9
Slave address – 7 bits
Write
10
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
10
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
18:11
19
18:11
19
27:20
28
20
27:21
28
Slave address – 7 bits
Read
29
29
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
37:30
38
39
Control Registers
Byte 0:Control Register 0
Bit
@Pup
Name
Description
7
1
CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
CPU[T/C]2_ITP/SRC[T/C]7 Output Enable
0 = Disable (Hi-Z), 1 = Enable
6
5
4
3
1
1
1
1
SRC[T/C]6
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]6 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Rev 1.0,November 22, 2006
Page 4 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
