CY28400-2
Table 4. Buffer Power-up State Machine
State
Description
0
1
3.3V Buffer power off
After 3.3V supply is detected to rise above 1.8V - 2.0V, the buffer enters state 1 and initiates a 0.2-ms–0.3-ms delay
2[1]
Buffer waits for PWRDWN deassertion (and waits for a valid clock on the SRC_IN input in PLL mode)
3[2,3,4] Once the PLL is locked to the SRC_IN input clock, the buffer enters state 3 and enables outputs for normal operation
Figure 5. Buffer Power-up State Diagram
SRC_STP Clarification
SRC_STP Assertion
The SRC_STP signal is an asynchronous input used for clean
stopping and starting the DIFT/C outputs. This input can be
Active HIGH or Active LOW based on the strapped value of
the OE_INV input. The SRC_STP signal is a debounced signal
in that its state must remain unchanged during two consec-
utive rising edges of DIFC to be recognized as a valid
assertion or deassertion. (The assertion and deassertion of
this signal is absolutely asynchronous.) In the case where the
output is disabled via OE control, the output will always be
tri-stated regardless of the SRC_STP Drive Mode register bit
state.
The impact of asserting the SRC_STP pin is that all DIF
outputs that are set in the control registers to stoppable via
assertion of SRC_STP are stopped after their next transition.
When the control register SRC_STP tri-state bit is
programmed to ‘0’, the final state of all stopped DIFT/C signals
is DIFT clock = High and DIFC = Low. There will be no change
to the output drive current values, DIFT will be driven high with
a current value equal 6 x Iref, and DIFC will not be driven.
When the control register SRC_STP three-state bit is
programmed to ‘1’, the final state of all stopped DIF signals is
low, both DIFT clock and DIFC clock outputs will not be driven.
Table 5. SRC_STP Functionality[4]
OE_INV
SRC_STP
DIFT
Normal
DIFC
Normal
Low
0
0
1
1
1
0
1
0
Iref * 6 or Float
Iref * 6 or Float
Normal
Low
Normal
Notes:
1. Disabling of the SRCT_IN input clock prior to assertion of PWRDWN is an undefined mode and not recommended. Operation in this mode may result in glitches
excessive frequency shifting.
2. The total power up latency from power-on to all outputs active is less than 1 ms (assuming a valid clock is present on SRC_IN input).
3. In PLL Mode, if power is valid and PWRDWN is deasserted but no input clocks are present on the SRC_IN input, DIF clocks will remain disabled. Only after valid
input clocks are detected, valid power, PWRDWN deasserted with the PLL locked and stable, are the DIF outputs enabled.
4. In the case where OE is asserted low, the output will always be three-stated regardless of SRC_STP drive mode register bit state.
Rev 1.0,November 21, 2006
Page 7 of 15
SPECTRALINEAR [ SPECTRALINEAR INC ]
