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CY28400ZXC-2 参数 Datasheet PDF下载

CY28400ZXC-2图片预览
型号: CY28400ZXC-2
PDF下载: 下载PDF文件 查看货源
内容描述: 100 MHz差分缓冲器,用于PCI Express和SATA [100 MHz Differential Buffer for PCI Express and SATA]
分类和应用: 逻辑集成电路光电二极管驱动PC
文件页数/大小: 15 页 / 238 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28400-2  
programmed to ‘0’, all clock outputs will be held with the DIFT  
pin driven high at 2 x Iref and DIFC tri-stated. However, if the  
control register PWRDWN Drive Mode bit is programmed to  
‘1’, then both DIFT and the DIFC are tri-stated.  
OE_INV  
PWRDWN  
Mode  
Power Down  
Normal  
0
0
1
1
0
1
0
1
Normal  
PWRDWN—Deassertion  
Power Down  
The power-up latency is less than 1 ms. This is the time from  
the deassertion of the PWRDWN pin or the ramping of the  
power supply or the time from valid SRC_IN input clocks until  
the time that stable clocks are output from the buffer chip (PLL  
locked). IF the control register PWRDWN Drive Mode bit is  
programmed to ‘1’, all differential outputs must be driven high  
in less than 300 Ps of the power down pin deassertion to a  
voltage greater than 200 mV.  
PWRDWN—Assertion  
When the power-down pin is sampled as being asserted by  
two consecutive rising edges of DIFC, all DIFT outputs will be  
held high or tri-stated (depending on the state of the control  
register drive mode and OE bits) on the next DIFC high to low  
transition. When the SMBus PWRDWN Drive Mode bit is  
PWRDWN  
DIFT  
DIFC  
Figure 1. PWRDWN Assertion Diagram, OE_INV = 0  
PWRDWN  
DIFT  
DIFC  
Figure 2. PWRDWN Assertion Diagram, OE_INV = 1  
Tstable  
<1 ms  
PWRDWN  
DIFT  
DIFC  
Tdrive_Pwrdwn#  
<300 µs, >200 mV  
Figure 3. PWRDWN Deassertion Diagram, OE_INV = 0  
Tstable  
<1 ms  
PWRDWN  
DIFT  
DIFC  
Tdrive_Pwrdwn#  
<300 µs, >200 mV  
Figure 4. PWRDWN Deassertion Diagram, OE_INV = 1  
Rev 1.0,November 21, 2006  
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