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CY28359 参数 Datasheet PDF下载

CY28359图片预览
型号: CY28359
PDF下载: 下载PDF文件 查看货源
内容描述: 273 MHz的6输出缓冲的DDR400的DIMM [273 MHz 6 Output Buffer for DDR400 DIMMS]
分类和应用: 双倍数据速率
文件页数/大小: 7 页 / 129 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28359  
Pin Description  
Pin  
Name  
BUF_INA,  
BUF_INB  
PWR  
I/O  
Description  
10  
2
VDD2.5  
I
Reference input from chipset. 2.5V input.  
13,15,20  
4,6,24  
DDRA[0:2]C  
DDRB[0:2]C  
VDD2.5  
VDD2.5  
VDD2.5  
O
O
O
Clock outputs. These outputs provide complementary  
copies of BUF_INA & BUF_INB, respectively.  
12,14,21  
3,5,25  
DDRA[0:2]T  
DDRB[0:2]T  
Clock outputs. These outputs provide copies of BUF_INA  
& BUF_INB, respectively.  
9
1
FB_OUTA  
FB_OUTB  
Feedback clock for chipset  
18  
SCLK  
VDD2.5  
VDD2.5  
I
I/O  
I
SMBus clock input. Has pull-up resistor  
SMBus data input. Has pull-up resistor  
Address Select Pin. Has pull-down resistor  
2.5V voltage supply  
19  
SDATA  
SEL_ADDR  
VDD2.5  
VSS  
26  
7,16,22,28  
8,11,17,23,27  
Ground  
controller. For Block Write/Read operation, the bytes must be  
accessed in sequential order from lowest to highest byte (most  
significant bit first) with the ability to stop after any complete  
byte has been transferred. For Byte Write and Byte Read  
operations, the system controller can access individual  
indexed bytes. The offset of the indexed byte is encoded in the  
command code, as described in Table 1.  
Serial Data Interface  
To enhance the flexibility and function of the clock synthesizer,  
a two-signal serial interface is provided. Through the Serial  
Data Interface, various device functions, such as individual  
clock output buffers, can be individually enabled or disabled.  
The registers associated with the Serial Data Interface  
initializes to their default setting upon power-up, and therefore  
use of this interface is optional. The interface can also be  
accessed during power down operation.  
The Block Write and Block Read protocol is outlined in Table 2  
while Table 3 outlines the corresponding Byte Write and Byte  
Read protocol.The slave receiver address is 11010010 (D2h)  
or 11011100 (DCh) depending on state of ADDRSEL.  
Data Protocol  
The clock driver serial protocol accepts Byte Write, Byte Read,  
Block Write and Block Read operation from any external I2C  
Table 1. Command Code Definition  
Bit  
Description  
7
0 = Block Read or Block Write operation  
1 = Byte Read or Byte Write operation  
(6:5) 01  
(4:0) Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be '00000'  
Rev 1.0,November 24, 2006  
Page 2 of 7