CY28354-400
Byte 22: Outputs Active/Inactive Register (1 = Active, 0 = Inactive), Default (Hi-z) = Active
Bit
@Pup
Pin #
Description
Bit 7
Bit 6
0
0
Input Threshold Control
00: Normal (1.25V)
01: 1.20V
10: 1.15V
11: 1.10V
Bit 5
Bit 4
Bit 3
0
0
1
17
3
FBOUTA Control, 0 = Enable, 1 = Disable
FBOUTB Control, 0 = Enable, 1 = Disable
30,
29
DDRBT5,
DDRBC5
Bit 2
Bit 1
Bit 0
1
1
1
32,
31
DDRBT4,
DDRBC4
42,
41
DDRBT3,
DDRBC3
44,
43
DDRBT2,
DDRBC2
Byte 23: Outputs Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit
@Pup
Pin #
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
7,
8
DDRBT1,
DDRBC1
1
1
1
1
1
1
1
5,
6
DDRBT0,
DDRBC0
36,
35
DDRAT5,
DDRAC5
38,
37
DDRAT4,
DDRAC4
21,
22
DDRAT3,
DDRAC3
19,
20
DDRAT2,
DDRAC2
13,
14
DDRAT1,
DDRAC1
11,
12
DDRAT0,
DDRAC0
Rev 1.0,November 22, 2006
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