CY28347
Byte 8: Silicon Signature Register (all bits are Read-only)
Bit
7
@Pup
Name
Revision_ID3
Revision_ID2
Revision_ID1
Revision_ID0
Vender_ID3
Vender_ID2
Vender_ID1
Vender_ID0
Description
0
0
0
0
1
0
0
0
Revision ID bit [3]
6
Revision ID bit [2]
5
Revision ID bit [1]
4
Revision ID bit [0]
3
Cypress’s Vendor ID bit [3]
Cypress’s VendorID bit [2]
Cypress’s Vendor ID bit [1]
Cypress’s Vendor ID bit [0]
2
1
0
Byte9: Dial-A-Frequency Control Register R
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
0
Reserved
6
R5, MSB
These bits are for programming the PLL’s internal R register. This access allows
the user to modify the CPU frequency at very high resolution (accuracy). All other
synchronous clocks (clocks that are generated from the same PLL, such as PCI)
remain at their existing ratios relative to the CPU clock.
5
R4
4
R3
3
R2
2
R1
1
R0
0
DAF_ENB
R and N register mux selection. 0=R and N values come from the ROM. 1=data is
load from DAF (I2C) registers.
Dial-a-Frequency Feature
Spread Spectrum Clock Generation (SSCG)
SMBus Dial-a-frequency feature is available in this device via
Byte7 and Byte9.
Spread Spectrum is enabled/disabled via SMBus register Byte
1, Bit 6.
P is a PLL constant that depends on the frequency selection
prior to accessing the Dial-a-Frequency feature.
Table 10. Spread Spectrum Table
Mode
SST1
SST0
% Spread
–1.5%
–1.0%
–0.7%
–0.5%
0.75%
0.5%
Table 9.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FS(4:0)
P
XXXXX
96016000
0.35%
0.25%
Rev 1.0,November 20, 2006
Page 8 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
