CY28347
Table 6. Byte Read and Byte Write Protocol (continued)
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code - 8 bits “1xxxxxxx” stands for byte
operation bit[6:0] of the command code represents
the offset of the byte to be accessed
11:18
Command Code - 8 bits “1xxxxxxx” stands for byte
operation bit[6:0] of the command code represents
the offset of the byte to be accessed
19
20:27
28
Acknowledge from slave
Data Byte from Master – 8 Bits
Acknowledge from slave
Stop
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address - 7 bits
Read
29
29
Acknowledge from slave
Data byte from slave - 8 bits
Not Acknowledge
Stop
30:37
38
39
Byte 0: Frequency Select Register
Bit
7
@Pup
0
Pin#
Name
Description
Reserved.
6
H/W Setting
H/W Setting
H/W Setting
0
21
10
1
FS2
FS1
FS0
For Selecting Frequencies see Table 1.
For Selecting Frequencies see Table 1.
For Selecting Frequencies see Table 1.
5
4
3
If this bit is programmed to “1,” it enables WRITES to bits (6:4,1) for
selecting the frequency via software (SMBus)
If this bit is programmed to a “0” it enables only READS of bits
(6:4,1), which reflect the hardware setting of FS(0:3).
2
1
0
H/W Setting
H/W Setting
H/W Setting
11
20
7
Reserved
FS3
Reserved
For Selecting frequencies in Table 1.
SELP4_K7#
Only for reading the hardware setting of the CPU interface mode,
status of SELP4_K7# strapping.
Byte 1: CPU Clocks Register
Bit
@Pup
Pin#
Name
Description
7
0
SSMODE
0 = Down Spread. 1 = Center Spread. See Table 10.
6
5
4
3
1
1
1
1
SSCG
1 = Enable (default). 0 = Disable
SST1
Select spread bandwidth. See Table 10.
Select spread bandwidth. See Table 10.
SST0
48,49
53,52
53,52
CPUCS_T/C_ EN#
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
2
1
1
0
CPUOD_T/C_EN#
1 = output enabled (running). 0 = output disable asynchronously
in a LOW state.
CPUT/C_PD_CNTRL
In K7 mode, this bit is ignored. In P4 mode, when PD# asserted
LOW, 0 = drive CPUT to 2xIref and CPUC LOW and
1 = three-state CPUT and CPUC.
0
1
11
MULT0
Only For reading the hardware setting of the Pin11 MULT0 value.
Byte 2: PCI Clock Register
Bit
@Pup
Pin#
Name
Description
7
0
PCI_DRV
PCI clock output drive strength 0 = Normal, 1 = increase the drive
strength 20%.
6
5
1
1
10
PCI_F
1 = output enabled (running). 0 = output disabled asynchronously
in a LOW state.
Reserved, set = 1.
Rev 1.0,November 20, 2006
Page 5 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
