CY28312B-2
Byte 6: Reserved Register (continued)
Bit
Name
Reserved
Reserved
Reserved
Reserved
Default
Description
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Byte 7: Reserved Register
Bit Name
Default
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 8: Vendor ID and Revision ID Register (Read-only)
Bit
Name
Revision_ID3
Revision_ID2
Revision_ID1
Revision_ID0
Vendor_ID3
Vendor_ID2
Vendor _ID1
Vendor _ID0
Default
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
0
0
0
Revision ID bit[3]
Revision ID bit[2]
Revision ID bit[1]
Revision ID bit[0]
Bit[3] of Cypress’s Vendor ID. This bit is read-only.
Bit[2] of Cypress’s Vendor ID. This bit is read-only.
Bit[1] of Cypress’s Vendor ID. This bit is read-only.
Bit[0] of Cypress’s Vendor ID. This bit is read-only.
Byte 9: System Reset and Watchdog Timer Register
Bit
Bit 7
Name
Reserved
Default
Description
0
0
Reserved
Bit 6
PCI_DRV
PCI clock output drive strength
0 = Normal
1 = High Drive
Bit 5
Bit 4
Reserved
0
0
Reserved
RST_EN_WD
This bit will enable the generation of a Reset pulse when a Watchdog timer time-out
occurs.
0 = Disabled
1 = Enabled
Bit 3
Bit 2
RST_EN_FC
0
0
This bit will enable the generation of a Reset pulse after a frequency change occurs.
0 = Disabled
1 = Enabled
WD_TO_STATUS
Watchdog Timer Time-out Status bit
0 = No time-out occurs (READ); Ignore (WRITE)
1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE)
Bit 1
Bit 0
WD_EN
0
0
0 = Stop and reload Watchdog timer
1 = Enable Watchdog timer. It will start counting down after a frequency change occurs.
Reserved
Reserved
Rev 1.0,November 21, 2006
Page 7 of 17
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