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CY28312B-2T 参数 Datasheet PDF下载

CY28312B-2T图片预览
型号: CY28312B-2T
PDF下载: 下载PDF文件 查看货源
内容描述: FTG的VIA ™ K7系列芯片组具有可编程输出频率 [FTG for VIA⑩ K7 Series Chipset with Programmable Output Frequency]
分类和应用:
文件页数/大小: 17 页 / 189 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CY28312B-2T的Datasheet PDF文件第1页浏览型号CY28312B-2T的Datasheet PDF文件第2页浏览型号CY28312B-2T的Datasheet PDF文件第4页浏览型号CY28312B-2T的Datasheet PDF文件第5页浏览型号CY28312B-2T的Datasheet PDF文件第6页浏览型号CY28312B-2T的Datasheet PDF文件第7页浏览型号CY28312B-2T的Datasheet PDF文件第8页浏览型号CY28312B-2T的Datasheet PDF文件第9页  
CY28312B-2  
Pin Definitions (continued)  
Pin  
Type  
Pin Name  
SDATA  
Pin No.  
Pin Description  
Data pin for SMBus circuitry.  
Clock pin for SMBus circuitry.  
31  
30  
40  
I/O  
I
SCLK  
VDD_CPU  
P
2.5V Power Connection. Power supply for CPU output buffers. Connect to  
2.5V.  
VDDQ_AGP  
VDDQ_PCI  
VDDQ_48MHz  
VDD_REF  
25  
P
P
P
P
3.3V Power Connection. Power supply for AGP output buffers. Connect to 3.3V.  
3.3V Power Connection. Power supply for PCI output buffers. Connect to 3.3V.  
3.3V Power Connection. Power supply for 48-MHz output buffers. Connect to 3.3V.  
15, 23  
5
1
3.3V Power Connection: Power supply for reference output buffers. Connect  
to 3.3V.  
VDD_Core  
33  
P
3.3V Power Connection: Power supply for PLL core. Connect to 3.3V.  
GND_REF,  
GND_48MHz,  
GND_PCI,  
GND_AGP,  
GND_Core,  
GND_CPU  
2, 8, 29, 32, 37,  
43  
G
Ground Connections: Connect all ground pins to the common system ground  
plane.  
controller. For block write/read operation, the bytes must be  
accessed in sequential order from lowest to highest byte with  
Serial Data Interface  
The CY28312B-2 features a two-pin, serial data interface that  
can be used to configure internal register settings that control  
particular device functions.  
the ability to stop after any complete byte has been trans-  
ferred. For byte/word write and byte read operations, system  
controller can access individual indexed byte. The offset of the  
indexed byte is encoded in the command code.  
Data Protocol  
The definition for the command code is defined in Table 1.  
The clock driver serial protocol supports byte/word write,  
byte/word read, block write and block read operations from the  
Bit  
Descriptions  
7
0 = Block read or block write operation  
1 = Byte/Word read or byte/word write operation  
6:0  
Byte offset for byte/word read or write operation. For block read or write operations, these bits  
need to be set at ‘0000000’.  
Table 1. Block Read and Block Write Protocol  
Block Write Protocol  
Block Read Protocol  
Description  
Bit  
1
Description  
Bit  
1
Start  
Start  
2:8  
9
Slave address – 7 bits  
Write  
2:8  
9
Slave address – 7 bits  
Write  
10  
Acknowledge from slave  
10  
Acknowledge from slave  
11:18  
Command Code – 8 bits  
‘00000000’ stands for block operation  
11:18  
Command Code – 8 bits  
‘00000000’ stands for block operation  
19  
20:27  
28  
Acknowledge from slave  
Byte Count – 8 bits  
19  
20  
Acknowledge from slave  
Repeat start  
Acknowledge from slave  
Data byte 0 – 8 bits  
21:27  
28  
Slave address – 7 bits  
Read  
29:36  
37  
Acknowledge from slave  
Data byte 1 – 8 bits  
29  
Acknowledge from slave  
Byte count from slave – 8 bits  
Acknowledge  
38:45  
46  
30:37  
38  
Acknowledge from slave  
Rev 1.0,November 21, 2006  
Page 3 of 17