CY28312B-2
Byte 2: Control Register 2 (continued)
Bit
Pin#
13
Name
Default
Description
Bit 2
Bit 1
Bit 0
PCI2
PCI1
PCI0
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
11
10
Byte 3: Control Register
Bit
Bit 7
Pin#
Name
PCI_F
Default
Description
9
1
1
0
1
1
0
1
1
(Active/Inactive)
(Active/Inactive)
Reserved
Bit 6
22
–
PCI9_E
Reserved
PCI8
Bit 5
Bit 4
21
46
–
(Active/Inactive)
(Active/Inactive)
Reserved
Bit 3
REF2
Bit 2
Reserved
REF1
Bit 1
47
48
(Active/Inactive)
(Active/Inactive)
Bit 0
REF0
Byte 4: Watchdog Timer Register
Bit
Pin#
Name
Reserved
Default
Description
Bit 7
Bit 6
–
–
0
0
Reserved
FS_Override
0 = Select operating frequency by FS[4:0] input pins
1 = Select operating frequency by SEL[4:0] settings
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
–
–
–
–
–
WD_TIMER4
WD_TIMER3
WD_TIMER2
WD_TIMER1
WD_TIMER0
1
1
1
1
1
These bits store the time-out value of the Watchdog
timer. The scale of the timer is determine by the
prescaler.
The timer can support a value of 150 ms to 4.8 sec
when the prescaler is set to 150 ms. If the prescaler is
set to 2.5 sec, it can support a value from 2.5 sec to 80
sec.
When the Watchdog timer reaches “0”, it will set the
WD_TO_STATUS bit.
Bit 0
–
WD_PRE_SCAL
ER
0
0 = 150 ms
1 = 2.5 sec
Byte 5: Control Register 5
Bit
Pin#
9
Name
Default
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Latched FS4 input
X
X
X
X
X
0
Latched FS[4:0] inputs. These bits are read-only.
7
Latched FS3 input
Latched FS2 input
Latched FS1 input
Latched FS0 input
Reserved
6
47
48
–
Reserved
–
Reserved
0
Reserved
–
SEL4
0
SW Frequency selection bits. See Table 4.
Byte 6: Reserved Register
Bit
Name
Reserved
Reserved
Reserved
Reserved
Default
Description
Bit 7
Bit 6
Bit 5
Bit 4
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Rev 1.0,November 21, 2006
Page 6 of 17
SPECTRALINEAR [ SPECTRALINEAR INC ]
